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USB Superspeed Peripherals

user_3616931
New Contributor

1. I add a new sensor  ov9281 that support raw10 mipi data in cyusb3064, but i find CX3 DMA cannot receive mipi data, No access to the CyCx3AppDmaCallback() function.and the mipi end can be measured with data,Why can't receive data?

  Below is my mipi configuration.

pastedImage_13.png

pastedImage_14.png

/* ov9281_RAW8_720p : 800p */

CyU3PMipicsiCfg_t ov9281_RAW8_720p = 

{

    CY_U3P_CSI_DF_RAW8,  /* CyU3PMipicsiDataFormat_t dataFormat */

    2,                          /* uint8_t numDataLanes */

    2, /* uint8_t pllPrd */

    89, /* uint16_t pllFbd */

    CY_U3P_CSI_PLL_FRS_250_500M, /* CyU3PMipicsiPllClkFrs_t pllFrs */ 

    CY_U3P_CSI_PLL_CLK_DIV_4, /* CyU3PMipicsiPllClkDiv_t csiRxClkDiv */

    CY_U3P_CSI_PLL_CLK_DIV_4, /* CyU3PMipicsiPllClkDiv_t parClkDiv */

    0,                 /* uint16_t mClkCtl */

    CY_U3P_CSI_PLL_CLK_DIV_2, /* CyU3PMipicsiPllClkDiv_t mClkRefDiv */

    1280,         /* uint16_t hResolution */

    50                         /* uint16_t fifoDelay */

};

pastedImage_17.png

we measured The  G6 and H5  find no signal ,it is looks like  MIPI-CSI2 config  problem?

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1 Solution
YangyangC_06
Employee

For a CX3 camera design, you could follow the procedure below to locate the root cause.

  1. You need to check whether all the power domains for CX3 and sensor are fine. Also you need to check all the clock sources.
  2. Please check if the sensor has a correct power on/reset procedure when the board is power on.
  3. After the firmware running, CX3 will start to write configuration bytes via I2C bus. You need to check if all the registers are written correctly.
  4. After step3, sensor should output the data on data lane and clock lane. Check the signals on these pins to see if the sensor works fine.
  5. In this step, you need to check if you make a correct MIPI input configuration. This is what you post in your question. There is one thing which you need take care of, you need to confirm the THS_zero and THS_prepare are correct.

Please first check this issue accordingly.

View solution in original post

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10 Replies
YangyangC_06
Employee

For a CX3 camera design, you could follow the procedure below to locate the root cause.

  1. You need to check whether all the power domains for CX3 and sensor are fine. Also you need to check all the clock sources.
  2. Please check if the sensor has a correct power on/reset procedure when the board is power on.
  3. After the firmware running, CX3 will start to write configuration bytes via I2C bus. You need to check if all the registers are written correctly.
  4. After step3, sensor should output the data on data lane and clock lane. Check the signals on these pins to see if the sensor works fine.
  5. In this step, you need to check if you make a correct MIPI input configuration. This is what you post in your question. There is one thing which you need take care of, you need to confirm the THS_zero and THS_prepare are correct.

Please first check this issue accordingly.

View solution in original post

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user_3616931
New Contributor

hi:    

     thank for you reply。

1  first we  check all CX3 clock sources is  correct.

check the sensor has a correct power on/reset procedure when the board is power on.

3  check the  sensor  registers are written correctly via I2C bus.

measure  sensor  output the mipi  data on data lane and clock lane is correct

We don't know how to change THS_zero and THS_prepare values.

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YangyangC_06
Employee

For the step 4, please upload the waveform screenshot.

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user_3616931
New Contributor

1.jpg2.jpg3.jpg4.jpg5.jpg6.jpg7.jpg8.jpg9.jpg

The first four are data single-terminal signal levels, where the D0/1_n line signal has a semi-high level when returning to HS mode in LP mode, and D0/1_p does not have this phenomenon! The middle four are the single terminal level of the clock signal, which is seen from the waveform as a continuous clock mode. The last one is a frame of data, and there's a line of data discontinuity.

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Keerthy
Moderator
Moderator

Hi,

  • Is the MIPI clock gated or continuous? If the sensor is streaming in continuous clock mode, follow the steps mentioned in question 13 of the following link:

          http://www.cypress.com/knowledge-base-article/cx3-hardware-frequently-asked-questions-kba9...

  • Print the MIPI CSI error counts over UART by using the API “CyU3PMipicsiGetErrors”. Check if any of the error count is non-zero. If yes, double check the sensor configuration.
  • Vary the ‘thsSettleDelay’ parameter of “CyU3PMipicsiSetPhyTimeDelay()” API to check if the sensor is streaming for any of the delay value. Keep the first parameter as 0x01 always.
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user_3616931
New Contributor

hi:   

    thank for you reply.

    Our MIPI is not a continuous clock we need to take the time to confirm.

    I test the program every five seconds call function CyU3PMipicsiGetErrors print Discovery is 0.

    I tried calling the function CyU3PMipicsiSetPhyTimeDelay() to change the delay value 0 to 0x7f but found no effect, the MIPI controller has not given the FV and LV signals.

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YangyangC_06
Employee

Hi,

Looks like the waveform of data is incorrect. Please check it again. Also please try to switch the clock to gate mode instead of continuous mode.

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user_3616931
New Contributor

Thank you for your advice.I'm trying to use gate clock now. we tested the LV and FV signals of the mipi-csi2. The figure below is what we measured.

微信图片_20181013210828.jpg

but when DMA calls function CyU3PDmaMultiChannelGetBuffer three times, the system hangs once,What could be the cause of this?

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user_3616931
New Contributor

I  find  call function CyU3PDmaMultiChannelCommitBuffer (chHandle, (DmaBuffer.count + CX3_UVC_PROD_HEADER), 0); return status is CY_U3P_ERROR_INVALID_SEQUENCE, What could be the cause of this?

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Keerthy
Moderator
Moderator

Possibly.

Can you please have a look into the following article: Invalid Sequence Error in Multi-Channel Commit Buffer - KBA218830 ?

It may be useful for you.

As mentioned in the article, please try to increase the DMA buffer size as much as possible.

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