AN65974

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jori_4613131
Level 2
Level 2
First like given

Hi, I am trying to immigrate FPGA example from AN65974 to the the board selling on-line, I got strange problems.

I made a few revisions shown bellow.

1. GPIO assignment accord to my board connection from FPGA(A7 series) to USB3014.

pastedImage_1.png

2.  I use almost the same code as the one in FPGA Source File for Xilinx. as you know I need to immigrate its IP to mine, I keep its mode to be Bulk Out for test.

3.  for firmware, I do not revise.

I got the following problems.

1. Single transmission always OK for BULK OUT, for all images tried.

2. After I send 2MB file, it depends, it somtimes failed returning 997 code, I found it has relation with specifi pattern of data sent, e.g. all zeros has less faults than 0-255-loop-data.

what's more, WIN7 behave better than WIN10, and DEBUG version of firmware behave better than RELEASE.

any adivces?

thanks
Jiayou

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3 Replies
Hemanth
Moderator
Moderator
Moderator
First like given First question asked 750 replies posted

Hi Jiayou,

Which application are you using on the Host to receive the data?

What problem do you see when 0-255-loop-data is sent?

Regards,

Hemanth

Hemanth
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Hi, Hemanth, thanks for your reply.

I use Control Center to send bulk data out to FPGA, this is actual case I want to implement.

I saw it sometimes failed with error code 997, and I ask local FAE for help, they ask for log info, and I got error as following from UART.

pastedImage_0.png

Thanks

Jiayou

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Hemanth
Moderator
Moderator
Moderator
First like given First question asked 750 replies posted

Hi Jiayou,

Please increase the transfer timeout on the Host and try.

Regards,

Hemanth

Hemanth
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