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{Updated based on comments]
Hi, I have managed to get the 720p AN75779 example working with my FPGA video source and the 16 bit GPIF. I now want to expand to 1080p at 30 fps, but I'm having trouble. I've made the following changes to uvc/glProbeCtrl, cyfyuvcdscr/CyFxUSBSSConfigDscr and to the GPIF state machine. I'm using these posts uvc fx3 an75779 GPIF switch 8 to 16 bit Change Resolution in FX3 UVC Camera - KBA220269 Configuring Buffer Sizes in AN75779 UVC Firmware – KBA90744 as a reference
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uvc.c
glProbeCtrl
0x00, 0x48, 0x3F, 0x00 /* Max video frame size in bytes*/ /* 1920 * 1080 * 2 bytes per Pixel*/
0x00, 0xC0, 0x00, 0x00 /*No of bytes device can rx in single payload*/ //changed to 48KB
in uvc.h
Changed CY_FX_UVC_STREAM_BUF_COUNT (2) //changed from 4
with changes dmaMultiConfig.count to 2 in uvc.c
cyfxuvcdscr.c
CyFxUSBSSConfigDscr[]
/*VS Frame descriptor */
0x80, 0x07 /*Width in pixel*/ /*0x780 = 1920*/
0x38, 0x04 /*Height in pixel*/ /*0x438 = 1080*/
0x00, 0x48, 0x3F, 0x00 /*Maximum video or still frame size in bytes*/ /*0x3F4800*/
GPIF Designer
Changed from a 8bit bus to a 16 bit.
Change LD_DATA_COUNT to 24567
Change LD_ADDR_COUNT to 24567
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Right now when I run the code, there's stream from my webcam software, but the YUV values are all mixed up (Getting blue and red randomly when I only want Red). On the Serial Debugger I get frequent "Commit Buffer Failure" messages.
Is there anything that I might have missed? Do I need to change the bit rate or do I need to change the Config for Full speed and High Speed as well as Superspeed? I increased the "payload" in glProbeCtrl in 48KB (0xC000) is there anywhere eleseI need to change that? Maybe in uvc.h?
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Edited:
Please try to the following two:
1. Increase the DMA buffer size to 36 * 1024 bytes and DMA buffer count to 3 while creating the DMA channel using CyU3PDmaMultiChannelCreate API
a. Change the 0x00, 0x90, 0x00, 0x00, /* No. of bytes device can rx in single payload = 36*1024 */ in probe control structures
b. Change the GPIF LD_DATA_COUNT and LD_ADDR_COUNT as per Configuring Buffer Sizes in AN75779 UVC Firmware – KBA90744
c. i.e. LD_DATA_COUNT = LD_ADDR_COUNT = ((36*1024 -12-4)/2) -1 = 18423
2. Increase the DMA buffer size to 48*1024 bytes and DMA buffer count to 2 while creating the DMA channel using CyU3PDmaMultiChannelCreate API
a. Change the 0x00, 0xC0, 0x00, 0x00, /* No. of bytes device can rx in single payload = 48 KB */ in probe control structures
b. Change the GPIF LD_DATA_COUNT and LD_ADDR_COUNT as per Configuring Buffer Sizes in AN75779 UVC Firmware – KBA90744
c. i.e. LD_DATA_COUNT = LD_ADDR_COUNT = ((48*1024 -12-4)/2) -1 = 24567
Note that 1920 x 1080 x 2 bytes per pixel at 30 fps can stream in only USB 3.0. Therefore the changes correspond to UVC descriptors, probe control structure applies to only Super speed configuration. However, the modification of GPIF counters applies irrespective of speed; High and Full speed operation does not need longer buffers.
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Thanks for the help. I'll try that tomorrow. Just to clarify, by count do you mean LD_DATA_COUNT and LD_ADDR_COUNT? And by increasing count to 3, do you mean 3KBs? I assume if I use the equation in the link you gave I will get that value. Thanks again
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Eoin,
I have edited the above response to provide better clarity.
Please check it.
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Ok I've done the following.
In uvc.c glprobe.
0x00, 0xC0, 0x00, 0x00 /*No of bytes device can rx in single payload*/ //changed to 48KB
in uvc.h
Changed CY_FX_UVC_STREAM_BUF_COUNT (2) //changed from 4
with changes dmaMultiConfig.count to 2 in uvc.c
In GPIF
LDR_DATA_COUNT and LDR_ADDR _COUNT to 24567.
Now the stream isn't freezing on the first frame. However I am still getting "Commit Buffer Failure". I'm changing the YUV values live and when I try to change the V value which should turn the image red, I get random lines of red and blue. So my signal is changing U and V values.
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Eoin,
Please measure the HSYNC, VSYNC and PCLK values and share it here.
Are you doing the DMA_RESET when there is Commitbuffer as did in AN75779?
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I measured HSYNC and VSYNC with an oscilloscope and a Logic analyzer.
H SYNC is 43.84 kHz or 22.81 us. It's 20 us high then 2.81us low
V Sync is 30.01 Hz or 33.33ms. It's 24.62 ms high, 8.6ms low.
HSYNC is low when VSYNC is low. Within the high part of VSYNC there are 1080 HSYNC periods. So I know that there 1080 line been written within one frame.
The PCLK clock is 96Mhz, I can't measure it on my logic analyzer, but takes 2 PCLK to write 2 pixels and 1920 / 96MHz = 20us. I'm confidence that these values are right.
I don't really understand what you mean by DMA_RESET. I have connected the FX3 RESET on CTRL5 to the reset input in my FPGA code. I measured the initial reset sent by the FX3 to the FPGA and it does reset the HSYNC and VSYNC values and the counters used set those values.
I am working from the AN75779 example code, and the only other change I'v made is disabling sensor.c/SensorInit. So I'm pretty sure that the DMA_RESET is the same.
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Eoin,
Please confirm wheter you are using the lasted UVC example code provided with AN75779 updated on 30th October 2017?
Search for CY_FX_UVC_DMA_RESET_EVENT in the AN75779. This event will be set in two cases: 1. Commitbuffer failure 2. Frame timer overflow.
Enable the DEBUG_PRINT_FRAME_COUNT Macro in AN75779, collect the UART Logs and share them here for further debugging.