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hi,
I am using Win7 + Suite USB 3.4.7 + 68013A PVX 56 + slave FIFO + (FPGA) Cyclone II,
I use CyConsole input" 1 2 3 4 5 6 7 8 9" , to EP2 , but I read "2 4 6 8" from EP6,
half data lose! anyone can help me ? thanks!
below is my firmware and verilog code:
=============================================================
// Called once at startup
CPUCS = 0x10; // CLKSPD[1:0]=10, for 48MHz operation, output CLKOUT
IFCONFIG = 0xE3;
REVCTL=0x01;
// 48 MHz internal clock source, drive IFCLK, synchronous slave FIFO mode
PINFLAGSAB = 0x08; // FLAGA - EP6 FULL flag
SYNCDELAY;
PINFLAGSCD = 0xE0; // FLAGD - EP2 Emtpy flag
SYNCDELAY;
PORTACFG |= 0x80;
EP4CFG = 0x02; //clear the valid bits on ep4 and ep8
SYNCDELAY;
EP8CFG = 0x02;
SYNCDELAY;
EP2CFG = 0xA2; // OUT, 512-bytes, 4x, bulk
SYNCDELAY;
EP6CFG = 0xE2; // IN, 512-bytes, 4x, bulk
SYNCDELAY;
FIFORESET = 0x80; // activate NAK-ALL to avoid race conditions
SYNCDELAY; // see TRM section 15.14
FIFORESET = 0x02; // reset, FIFO 2
SYNCDELAY; //
FIFORESET = 0x04; // reset, FIFO 4
SYNCDELAY; //
FIFORESET = 0x06; // reset, FIFO 6
SYNCDELAY; //
FIFORESET = 0x08; // reset, FIFO 8
SYNCDELAY; //
FIFORESET = 0x00; // deactivate NAK-ALL
// handle the case where we were already in AUTO mode...
// ...for example: back to back firmware downloads...
SYNCDELAY; //
EP2FIFOCFG = 0x00; // AUTOOUT=0, WORDWIDE=0
// core needs to see AUTOOUT=0 to AUTOOUT=1 switch to arm endp's
SYNCDELAY; //
EP2FIFOCFG = 0x10; // AUTOOUT=1, WORDWIDE=0
SYNCDELAY; //
EP6FIFOCFG = 0x0C; // AUTOIN=1, ZEROLENIN=1, WORDWIDE=0, INFM = 1;
SYNCDELAY;
=======================================================================================
module fpga_master
(
input clk,
input rst_n,
input flaga, //EP2 empty flag
input flagd, // EP6 full flag
output reg [1:0] faddr,
output reg sloe,
output reg slrd,
output reg slwr,
inout [7:0]fdata,
output led,
output beep
);
(* noprune *)reg [25:0] counter;
assign led =counter[25];
assign beep =1;
reg link = 0; //link控制三态门
(* noprune *)reg [7:0]fdata_reg = 0;
assign fdata = link ? fdata_reg:8'bz;
(* noprune *)reg [3:0] state = 0;
(* noprune *)reg [31:0] recv_count = 0;
(* noprune *)reg [31:0] send_count = 0;
(* noprune *)reg [7:0] fifodata = 0;
always@(posedge clk)
begin
counter <= counter + 26'b1;
end
(* noprune *) reg [7:0] temp[15:0];
always@(posedge clk)
begin
case(state)
0:
begin
faddr <= 2'b00;
sloe <= 0; // IDLE STATE
link <= 0;
slrd <= 1;
slwr <= 1;
state <= 1;
end
1:
begin
if(flaga == 1) // not empty
begin
slrd <= 0;
state <= 2;
end
else
begin
slrd <= 1;
state <= 0;
end
end
2:
begin
fifodata = fdata;
temp[recv_count] = fdata;
recv_count = recv_count +1;
faddr <= 2'b10; // ep6
link <= 1;
sloe <= 1;
state <= 3;
end
3:
begin
if(flagd == 1) // not full
state <= 4;
else
state <= 3;
fdata_reg <= fifodata;
end
4:
begin
slwr <= 0;
send_count <= send_count +1;
state <= 0;
end
default:
state<=0;
endcase
end
endmodule
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Hi Wanta,
From your description, I understood that you are transferring some data from Cy Console to FX2LP EP2 and then your FPGA is reading this data.
Once you receive this data in FPGA, you are writing it back to FX2 EP6 and then you are trying to read this data using Cy Console. Please correct me if I am wrong.
From the behavior that you are observing, it is looking like you are missing every alternate sample of data. Check the data that you received in the FPGA to find out whether you are missing that sample while reading or during writing that back to EP6.
Regards,
sai krishna.
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Hi,RSKV
Thank you for reply, You are right, I use fpga loopback FX2LP, using salve fifo x8
I watch register when fpga read byte from FX2LP, a byte will losed when read from EP2, EP6 is filled right
It looks like read one word instead byte, but I config EP2FIFOCFG = 0x10;
Does need power off then power on FX2LP when I download new firmware?
thanks
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Yes, you need to reset the device to download new firmware.
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Thank you very much!
Maybe my FX2LP is broken 😞
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Please let me know the reason why you are thinking that FX2LP is broken.
Are you unable to download the code now?.
Regards,
sai krishna.