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USB Low-Full-High Speed Peripherals

gean_3054931
Contributor II

Hello,

what is the minimum initial ifclk clock cycles in order to sample data lines in fx2lp?

after how many clcok cycles from the master,fx2lp is going to sample data lines in slavefifo interface?

regards,

geetha.

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1 Solution
Sananya_14
Moderator
Moderator

Hello Geetha,

The IFCLK cycles will be enabled by SLWR, SLOE and SLRD assertion in synchronous mode for data sampling. While writing to the slave FIFO interface, data will be sampled by FX2LP on the rising edge of the next clock cycle after SLWR is asserted.

Best Regards,

Sananya

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Sananya_14
Moderator
Moderator

Hello Geetha,

The IFCLK cycles will be enabled by SLWR, SLOE and SLRD assertion in synchronous mode for data sampling. While writing to the slave FIFO interface, data will be sampled by FX2LP on the rising edge of the next clock cycle after SLWR is asserted.

Best Regards,

Sananya

View solution in original post

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