USB low-full-high speed peripherals Forum Discussions

The FAQs mention that it is acceptable to apply VCCIO before VCC for CY7C65213:

USB-Serial Bridge Controller FAQs - KBA224054

Does this imply that for CY7C65211 it is ok to apply VCCIO before VBUS?

We are considering to use the CY7C65211 in a battery-powered design with 1.8 V IO levels.

We can only supply VBUS from the actual USB port (no other 3.3V or 5V source available),

but could sequence VCCIO with respect to VBUS at best in software (so VCCIO starts a few ms after VBUS)

or simply keep it on at all times (VCCIO is present when VBUS is not).

Is either of those configurations acceptable as long as we ensure XRES is kept low until both rails are stable?

I have a project that I am developing using the FX2 platform to read an I2C based encoders.  The system will host five different encoders which are read by the I2C bus and I would like to read their data buffer and place into a buffer to be read back by the computer when you do a bulk read.  This way each transaction on the USB bus yields the buffer contents of all five encoders.  I was trying to write the return of EZUSBReadI2C into EP2FIFOBUF but EP2FIFOBUF won't accept the data.

Helo

The customer has already used CY7C68013A on Android OS, but thye are investigating to use it on Windows10. It is necessary to correspond to the customer-specific custom VID and PID set in CY7C68013A with the Win driver prepared for CY7C68013A. Although it is possible to change the driver's Inf file according to the procedure of Cypress application note, the driver signature will be removed when the change is made, so in Win10 it is not possible to install the driver properly.
Therefore, please tell us about the following

Q1)  How to get the signature of custom VID and PID driver?
Q2)  How to resell this driver by our customer?

Best Regards

Arai

Does GPIF work for streaming applications too?

Also, I have tried to add a GPIF file to the standard bulkloop program given in the development kit.

I get the following message when I build the target.

*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS

    SEGMENT: ?PR?GPIFINIT?GPIF

Can any one help me as what to do ?

Thanks,

The discussion is locked and will be rewritten. When measuring the CC pin, the result is as follows.

The normal board has a 1.1V waveform, but the abnormal board does not.

I referred AN61345 - Designing with EZ-USB® FX2LP™ Slave FIFO Interface and

I followed Chapter 4.2 Stream IN Transfers and I simulate the FPGA VHDL source code to perform stream IN data transfers.

the enable signal for the FIFO‟s output driver - SLOE  doesn't change. I shared screenshot for my simulation result.

Data Stream IN State Diagram : flagd == 1 and sync == 1 are Okay.in state diagram SLOE =1 in both state.  why SLOE doesn't change?

Thanks

Esakki

Hello,

I'm having problems with mounting USB flash drive in this host controller.  It works most of the time but occasionally does not.  I noticed the times it is not mounting is at booting up embedded device.

I have modified VID,PID in bulkLoop, a firmware routine in the development kit.

Then I added my modified VID and PID in the.INF file of the development kit

Drivers can be identified in device Manager after installation

But it's not recognized in the Control Center

There is also no way to read the modified VID and PID in CyConsole

Hi,

This KBA:

https://www.cypress.com/comment/390351

states that there is double buffering with the serial interface.

Is there any further documentation on how this works? Is there an app-note with an according firmware where I can take suggestions for my own firmware?

I only have found examples where writing a byte in the outbuf just sends one byte and you have to check the sent status before sending the next byte, or examples where you have to start the reading of one byte every time and have to move the transferred byte before the next byte can be read.

Best Regards,

Frank