USB low-full-high speed peripherals Forum Discussions

I developed a software for CY7C64315 and tested with CY3660 Development Kit.
I use a MiniProg1 to program the development board and everything worked fine.

Now, I'm trying to program a chip CY7C64315 using Miniprog1 and ISSP(5pin connector), but the PSoC-Programmer software  can't acquire the device to program the HEX file into it.

Is there any incompatibility with Miniprog1 and CY7C64315?
Any help and advice would be appreciated.

Regards,
@anne_4609456

Hi Infineon

The CY7C65213 Driver (Win 10 和 Server 2012 OS )can't download from Infineon website , Can you help to provide is for us direct , Thank !! 

Infineon website as below:

https://www.infineon.com/cms/en/product/universal-serial-bus-usb-power-delivery-controller/peripheral-controllers/usb-serial-bridge-controller/cy7c65213-28pvxi/#!tools

Hi

I have observed that on boot up FlagB of FX2LP device in our application is going HIGH for sometime (approximately 288 millisecond), is that expected behavior of device?

Can we make it so that it doesn't go HIGH at boot up?

Also sometime while using our system with VLC for streaming, when we stop and start the stream again no data is visible on the display. Please suggest some of the possible issues that might have happened.

Hi,

To implement a Firmware Update Function in our tools, we use the Vendor Command 0xA0 to download and verify the internal RAM (MAIN and DATA). 

Verification of the RAM does not work if we ask a large number of bytes to read. We need to split. But we do not understood why  ..

Is there any limitations in size for the VC 0xA0 ?

Thanks.

Hello,

We are using CY7C65215-32LTX in our board as USB2UART bridge, we are using SCB0 only (to get 3M baud) and we face two issues:
a) We configured the system to 3Mbit (including RTS/CTS)but we are getting max baud rate of 2.1Mbit (single direction form UART to USB ) instead of 2.4Mbit  (decreasing all the start stop bits etc from 3Mbit).
We are using updated Windows driver 3.13.0.84

b) Beside the baud rate issue if we are trying to send commands (USB to UART direction) during the 2.1Mbit data (describe in question#1) we are missing several bits .

Thanks you

Efi

Hi,

I use a USB test suite from USB.ORG onto my FX2LP18 device (with our Firmware).

All Tests are PAS, with one exception .

The test FAILS onto one recommandations concerning MaxPacketSize of Endpoint Buffer that need to be 0x200 (512).

We use EP6 as a 1024 Bytes Buffer, so we described it as a 0x400 in the descrptor.

All our software works perfectly with this configuration.

Is there any drawbacks to use such Value of 1024 (instead of 512) andso not respecting the USB 2.0 FS recommandations ?

I am designing a circuit that uses the CY7C68013A as a USB peripheral controller.

I have a  question below.

According to section 7.1.7.3 in the USB 2.0 specification, Figure 7-29, when the VBUS reaches 4.01V, the device needs to pull up the D + line within 100ms.

If the circuit configuration shown in the attached file is used, can our circuit meet the above USB 2.0 specifications?

Hi,

I am looking at using the CY7C65213 for replacing a different device. The PCB is already manufactured and has one of the Do Not Use Pins on the CY7C65213 grounded. Is it safe to ground the Do Not Use pins? Specifically pin  on the -pin QFN package.

hello world,

im having a dvb tuner streaming over fx2lp slave IN to PC application.

when changing tv-channels the fx2lp gets a "hickup" not sending more data to PC.

i am monitoring the EP2STAT reg for EPfull and the EPprogrammable flags.

The FLAGA is output to a Pin CTL0 and toggles nicly when streaming.

Changing channel or turn off streaming gets FLAGA stay high (telling fifo full) and the EPfull bit also is on.

alright, i tryed to reset this situation by doing a FIFO-RESET sequence :

for (i=0;i<20;i++)
{
FIFORESET = 0x80; // activate NAK-ALL to avoid race conditions. ie. NAK all transfers
SYNCDELAY; // see TRM section 15.14

EP2CFG = 0x00; //switching to manual mode
SYNCDELAY;

FIFORESET = 0x82; // reset, FIFO 2
SYNCDELAY; //
FIFORESET = 0x82; // reset, FIFO 2
SYNCDELAY; //

EP2CFG = 0xE0; //switching back to auto mode
SYNCDELAY;

FIFORESET = 0x00; // deactivate NAK-ALL, resume normal operation
SYNCDELAY;
}

No chance, the FLAGA and th efull flag stay on, even when tuner is not streaming any more.

this is a beast 😉