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USB Low-Full-High Speed Peripherals

Anonymous
Not applicable

 Hi 

   

What happen slavefifo's flagd low and slwr low ?

   

Actually sensor's stream data flow cannot control. 

   

So what am i supposed to handle of this case?

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8 Replies
Anonymous
Not applicable

 Hi,

   

AN65974 would be helpful for you.

   

-PRJI

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Anonymous
Not applicable

 Hi,

   

Please ignore previous post.

   

Could you please elaborate your query.

   

-PRJI

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Anonymous
Not applicable

 What happen slavefifo's flagd low and slwr low?

   

   
        
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Anonymous
Not applicable

  What happen slavefifo's flagd low and slwr low?

   

   
        
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Anonymous
Not applicable

 Hi,

   

Please paste TD_init() part of your firmware.

   

-PRJI

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Anonymous
Not applicable

 void TD_Init( void )

   

{ // Called once at startup

   

 

   

 

   

CPUCS = 0x10; // CLKSPD[1:0]=10, for 48MHz operation, output CLKOUT

   

 

   

 

   

  PINFLAGSAB = 0x08; // FLAGA - indexed, FLAGB - EP8FF

   

  SYNCDELAY;

   

  PINFLAGSCD = 0xE0; // FLAGC - EP4EF, FLAGD - indexed

   

  SYNCDELAY;

   

  PORTACFG |= 0x80;

   

  SYNCDELAY;

   

// IFCONFIG = 0xE3; // for async? for sync?

   

  SYNCDELAY;

   

 

   

 

   

 

   

  // IFCLKSRC=0   , FIFOs !executes on external clk source 

   

  // xMHz=0       , don't care since IFCLKSRC=0

   

  // IFCLKOE=0    , Don't drive IFCLK pin signal at 48MHz

   

  // IFCLKPOL=0   , (Don't) invert IFCLK spin signal from internal clk

   

  // ASYNC=0      , master samples synchronous

   

  // GSTATE=1     , Don't drive GPIF states out on PORTE[2:0], debug WF

   

  // IFCFG[1:0]=11, FX2 in slave FIFO mode

   

 

   

 

   

  // Registers which require a synchronization delay, see section 15.14

   

  // FIFORESET        FIFOPINPOLAR

   

  // INPKTEND         OUTPKTEND

   

  // EPxBCH:L         REVCTL

   

  // GPIFTCB3         GPIFTCB2

   

  // GPIFTCB1         GPIFTCB0

   

  // EPxFIFOPFH:L     EPxAUTOINLENH:L

   

  // EPxFIFOCFG       EPxGPIFFLGSEL

   

  // PINFLAGSxx       EPxFIFOIRQ

   

  // EPxFIFOIE        GPIFIRQ

   

  // GPIFIE           GPIFADRH:L

   

  // UDMACRCH:L       EPxGPIFTRIG

   

  // GPIFTRIG

   

  

   

  // Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...

   

  //      ...these have been replaced by GPIFTC[B3:B0] registers

   

 

   

 

   

  

   

  // EP4 512 BULK OUT 4x

   

 // SYNCDELAY;                    // see TRM section 15.14

   

 EP4CFG = 0x02;                // BUF[1:0]=00 for 2x buffering

   

  

   

      // EP8 512 BULK IN 4x

   

 // SYNCDELAY;                    // 

   

 EP8CFG = 0x02;                // BUF[1:0]=00 for 2x buffering

   

 

   

  // EP2 and EP6 are not used in this implementation...

   

  SYNCDELAY;                    // 

   

  EP2CFG = 0xA0;                // clear valid bit

   

  SYNCDELAY;                    // 

   

  EP6CFG = 0xE0;                // clear valid bit

   

 

   

 

   

  SYNCDELAY;

   

  FIFORESET = 0x80;             // activate NAK-ALL to avoid race conditions

   

  SYNCDELAY;                    // see TRM section 15.14

   

  FIFORESET = 0x02;             // reset, FIFO 2

   

  SYNCDELAY;                    // 

   

  FIFORESET = 0x04;             // reset, FIFO 4

   

  SYNCDELAY;                    // 

   

  FIFORESET = 0x06;             // reset, FIFO 6

   

  SYNCDELAY;                    // 

   

  FIFORESET = 0x08;             // reset, FIFO 8

   

  SYNCDELAY;                    // 

   

  FIFORESET = 0x00;             // deactivate NAK-ALL

   

 

   

 

   

  // handle the case where we were already in AUTO mode...

   

  // ...for example: back to back firmware downloads...

   

  SYNCDELAY;                    // 

   

  EP2FIFOCFG = 0x00;            // AUTOOUT=0, WORDWIDE=1

   

  

   

  // core needs to see AUTOOUT=0 to AUTOOUT=1 switch to arm endp's

   

  

   

  SYNCDELAY;                    // 

   

  EP2FIFOCFG = 0x10;            // AUTOOUT=1, WORDWIDE=1

   

  

   

  SYNCDELAY;                    // 

   

  EP6FIFOCFG = 0x4C;            // AUTOIN=1, ZEROLENIN=1, WORDWIDE=1

   

 

   

  SYNCDELAY;

   

 

   

// Rwuen = TRUE; // Enable remote-wakeup

   

/*

   

OEA = 0x80; // set PA7 as output port 

   

LED = OFF;

   

 

   

OEB = 0xFF; // set PortB as output port 

   

IOB = 0x00; // All LED Off*/

   

 

   

/*

   

//OEA =0x01;

   

//IOA=0x01; //0x00; //LED ON 0x00 // 0x01 is off

   

 

   

if(OEA & 0x02)

   

{

   

OEA =0x01;

   

IOA=0x0f; 

   

}

   

*/

   

 

   

//////For stable DATA, IFCLOCK need  setup time that's it's need to INVCLK

   

 

   

 

   

OEA |= 0x09; //for tmp_rst    ----____----

   

IOA = 0x08;

   

 

   

// OEA |= 0x01; //default LED ON

   

IOA = 0x00; ////default LED ON 0x00 is OFF // 0x01 is ON

   

}

   
        
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Anonymous
Not applicable

 Hi,

   

 The FLAGD pin operates in Fixed mode only. Please refer section 9.2.4 FIFO Flag Pins (FLAGA, FLAGB, FLAGC, FLAGD) of      http://www.cypress.com/?docID=27095

   

-PRJI

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Anonymous
Not applicable

 I don't understand exactly 

   

Waht am i change in my F/W code?

   

 

   

   

#pragma NOIV                    // Do not generate interrupt vectors

   

//-----------------------------------------------------------------------------

   

//   File:      slave.c

   

//   Contents:  Hooks required to implement USB peripheral function.

   

//              Code written for FX2 REVE 56-pin and above.

   

//              This firmware is used to demonstrate FX2 Slave FIF

   

//              operation.

   

//   Copyright (c) 2003 Cypress Semiconductor All rights reserved

   

//-----------------------------------------------------------------------------

   

#include "fx2.h"

   

#include "fx2regs.h"

   

#include "fx2sdly.h"            // SYNCDELAY macro

   

 

   

//#include "iic.h"

   

//#include "i2c_sw.h"

   

//#include "cyanfwserial.h"

   

//#include "gpio.h"

   

extern BOOL GotSUD; // Received setup data flag

   

extern BOOL Sleep;

   

extern BOOL Rwuen;

   

extern BOOL Selfpwr;

   

 

   

BYTE Configuration; // Current configuration

   

BYTE AlternateSetting; // Alternate settings

   

BOOL done_frm_fpga = 0;

   

 

   

//-----------------------------------------------------------------------------

   

// Constants

   

//-----------------------------------------------------------------------------

   

#define VR_UPLOAD 0xc0

   

#define VR_DOWNLOAD 0x40

   

#define VR_EEPROM 0xa2 // loads (uploads) small EEPROM

   

#define VR_RAM 0xa3 // loads (uploads) external ram

   

#define VR_GET_CHIP_REV 0xa6 // Rev A, B = 0, Rev C = 2 // NOTE: New TNG Rev

   

#define VR_RENUM    0xa8 // renum

   

#define VR_DB_FX    0xa9 // Force use of double byte address EEPROM (for FX)

   

#define VR_I2C_100      0xaa // put the i2c bus in 100Khz mode

   

#define VR_I2C_400      0xab // put the i2c bus in 400Khz mode

   

 

   

WORD wIndex;

   

WORD wValue;

   

 

   

 

   

#define VENDOR_CMD1 0xda

   

#define VENDOR_CMD2 0xdb

   

 

   

#define SERIAL_ADDR 0x50

   

#define EP0BUFF_SIZE 0x40

   

 

   

 

   

BYTE xdata Cmd1[4];

   

BYTE xdata Cmd2[4];

   

BYTE xdata Cmd3[4];

   

 

   

#define GET_CHIP_REV() 4//((CPUCS >> 4) & 0x00FF) // EzUSB Chip Rev Field

   

 

   

//-----------------------------------------------------------------------------

   

// Global Variables

   

//-----------------------------------------------------------------------------

   

BYTE DB_Addr; //TPM Dual Byte Address stat

   

BYTE I2C_Addr; //TPM I2C address

   

 

   

//-----------------------------------------------------------------------------

   

// Prototypes

   

//-----------------------------------------------------------------------------

   

//void EEPROMWrite(WORD addr, BYTE length, BYTE xdata *buf); //TPM EEPROM Write

   

//void EEPROMRead(WORD addr, BYTE length, BYTE xdata *buf);  //TPM EEPROM Read

   

 

   

//-----------------------------------------------------------------------------

   

// Task Dispatcher hooks

   

// The following hooks are called by the task dispatcher.

   

//-----------------------------------------------------------------------------

   

 

   

void TD_Init( void )

   

{ // Called once at startup

   

 

   

 

   

CPUCS = 0x10; // CLKSPD[1:0]=10, for 48MHz operation, output CLKOUT

   

 

   

 

   

  PINFLAGSAB = 0x08; // FLAGA - indexed, FLAGB - EP8FF

   

  SYNCDELAY;

   

  PINFLAGSCD = 0xE0; // FLAGC - EP4EF, FLAGD - indexed

   

  SYNCDELAY;

   

  PORTACFG |= 0x80;

   

  SYNCDELAY;

   

// IFCONFIG = 0xE3; // for async? for sync?

   

  SYNCDELAY;

   

 

   

 

   

 

   

  // IFCLKSRC=0   , FIFOs !executes on external clk source 

   

  // xMHz=0       , don't care since IFCLKSRC=0

   

  // IFCLKOE=0    , Don't drive IFCLK pin signal at 48MHz

   

  // IFCLKPOL=0   , (Don't) invert IFCLK spin signal from internal clk

   

  // ASYNC=0      , master samples synchronous

   

  // GSTATE=1     , Don't drive GPIF states out on PORTE[2:0], debug WF

   

  // IFCFG[1:0]=11, FX2 in slave FIFO mode

   

 

   

 

   

  // Registers which require a synchronization delay, see section 15.14

   

  // FIFORESET        FIFOPINPOLAR

   

  // INPKTEND         OUTPKTEND

   

  // EPxBCH:L         REVCTL

   

  // GPIFTCB3         GPIFTCB2

   

  // GPIFTCB1         GPIFTCB0

   

  // EPxFIFOPFH:L     EPxAUTOINLENH:L

   

  // EPxFIFOCFG       EPxGPIFFLGSEL

   

  // PINFLAGSxx       EPxFIFOIRQ

   

  // EPxFIFOIE        GPIFIRQ

   

  // GPIFIE           GPIFADRH:L

   

  // UDMACRCH:L       EPxGPIFTRIG

   

  // GPIFTRIG

   

  

   

  // Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...

   

  //      ...these have been replaced by GPIFTC[B3:B0] registers

   

 

   

 

   

  

   

  // EP4 512 BULK OUT 4x

   

 // SYNCDELAY;                    // see TRM section 15.14

   

 EP4CFG = 0x02;                // BUF[1:0]=00 for 2x buffering

   

  

   

      // EP8 512 BULK IN 4x

   

 // SYNCDELAY;                    // 

   

 EP8CFG = 0x02;                // BUF[1:0]=00 for 2x buffering

   

 

   

  // EP2 and EP6 are not used in this implementation...

   

  SYNCDELAY;                    // 

   

  EP2CFG = 0xA0;                // clear valid bit

   

  SYNCDELAY;                    // 

   

  EP6CFG = 0xE0;                // clear valid bit

   

 

   

 

   

  SYNCDELAY;

   

  FIFORESET = 0x80;             // activate NAK-ALL to avoid race conditions

   

  SYNCDELAY;                    // see TRM section 15.14

   

  FIFORESET = 0x02;             // reset, FIFO 2

   

  SYNCDELAY;                    // 

   

  FIFORESET = 0x04;             // reset, FIFO 4

   

  SYNCDELAY;                    // 

   

  FIFORESET = 0x06;             // reset, FIFO 6

   

  SYNCDELAY;                    // 

   

  FIFORESET = 0x08;             // reset, FIFO 8

   

  SYNCDELAY;                    // 

   

  FIFORESET = 0x00;             // deactivate NAK-ALL

   

 

   

 

   

  // handle the case where we were already in AUTO mode...

   

  // ...for example: back to back firmware downloads...

   

  SYNCDELAY;                    // 

   

  EP2FIFOCFG = 0x00;            // AUTOOUT=0, WORDWIDE=1

   

  

   

  // core needs to see AUTOOUT=0 to AUTOOUT=1 switch to arm endp's

   

  

   

  SYNCDELAY;                    // 

   

  EP2FIFOCFG = 0x10;            // AUTOOUT=1, WORDWIDE=1

   

  

   

  SYNCDELAY;                    // 

   

  EP6FIFOCFG = 0x4C;            // AUTOIN=1, ZEROLENIN=1, WORDWIDE=1

   

 

   

  SYNCDELAY;

   

 

   

// Rwuen = TRUE; // Enable remote-wakeup

   

/*

   

OEA = 0x80; // set PA7 as output port 

   

LED = OFF;

   

 

   

OEB = 0xFF; // set PortB as output port 

   

IOB = 0x00; // All LED Off*/

   

 

   

/*

   

//OEA =0x01;

   

//IOA=0x01; //0x00; //LED ON 0x00 // 0x01 is off

   

 

   

if(OEA & 0x02)

   

{

   

OEA =0x01;

   

IOA=0x0f; 

   

}

   

*/

   

 

   

//////For stable DATA, IFCLOCK need  setup time that's it's need to INVCLK

   

 

   

 

   

OEA |= 0x09; //for tmp_rst    ----____----

   

IOA = 0x08;

   

 

   

// OEA |= 0x01; //default LED ON

   

IOA = 0x00; ////default LED ON 0x00 is OFF // 0x01 is ON

   

}

   

 

   

 

   

void TD_Poll( void )

   

{ // Called repeatedly while the device is idle

   

// int i;

   

 

   

// if (SETUPDAT[2] == 0x01 && (SETUPDAT[4] == 0xf0) )

   

if (SETUPDAT[4] == 0x50 )

   

   

/*

   

for(i=0; i<100; i++)

   

{

   

 

   

SYNCDELAY;

   

OEA |= 0x09;

   

IOA = 0x00;

   

}

   

SYNCDELAY;

   

*/

   

}

   

OEA |= 0x09;

   

IOA = 0x08;

   

 

   

   

 

   

   

/*

   

if(SETUPDAT[4] == 0x51) //LED on

   

{

   

OEA =0x01;

   

IOA=0x00;

   

}

   

if(SETUPDAT[4] == 0x50)  

   

{

   

OEA =0x01;

   

IOA=0x01;

   

 

   

// IFCONFIG = 0xE3;

   

}

   

*/

   

 

   

 

   

if( ((IOA & 0x02)==0x02) )

   

{

   

done_frm_fpga = 1;

   

// IOA =0x00;

   

// IOA=0x01; //output 1 on PC.0...SYNC signal is HIGH 

   

}

   

if ((done_frm_fpga) && ((IOA & 0x02)==0x02))

   

{

   

IOA = 0x08;

   

 

   

IFCONFIG = 0x13;   //need to inversion clock

   

   

SYNCDELAY;

   

//If done ? LED OFF

   

//IOA|=0x00; //output 1 on PC.0...SYNC signal is HIGH 

   

SYNCDELAY;

   

done_frm_fpga = 0;

   

}

   

 

   

 

   

 

   

 

   

 

   

 

   

/*

   

if(SETUPDAT[4] == 0x51)

   

{

   

OEA =0x01;

   

IOA=0x01;

   

}

   

if(SETUPDAT[4] == 0x50)  //LED on

   

{

   

OEA =0x01;

   

IOA=0x00;

   

}

   

*/

   

 

   

 

   

}

   

 

   

 

   

 

   

BOOL TD_Suspend( void )          

   

{ // Called before the device goes into suspend mode

   

   return( TRUE );

   

}

   

 

   

BOOL TD_Resume( void )          

   

{ // Called after the device resumes

   

CPUCS = 0x10;//2;

   

   return( TRUE );

   

}

   

 

   

//-----------------------------------------------------------------------------

   

// Device Request hooks

   

//   The following hooks are called by the end point 0 device request parser.

   

//-----------------------------------------------------------------------------

   

BOOL DR_GetDescriptor( void )

   

{

   

   return( TRUE );

   

}

   

 

   

BOOL DR_SetConfiguration( void )   

   

{ // Called when a Set Configuration command is received

   

  

   

  if( EZUSB_HIGHSPEED( ) )

   

  { // ...FX2 in high speed mode

   

    EP6AUTOINLENH = 0x02;

   

    SYNCDELAY;

   

    EP8AUTOINLENH = 0x02;   // set core AUTO commit len = 512 bytes

   

    SYNCDELAY;

   

    EP6AUTOINLENL = 0x00;

   

    SYNCDELAY;

   

    EP8AUTOINLENL = 0x00;

   

  }

   

  else

   

  { // ...FX2 in full speed mode

   

    EP6AUTOINLENH = 0x00;

   

    SYNCDELAY;

   

    EP8AUTOINLENH = 0x00;   // set core AUTO commit len = 64 bytes

   

    SYNCDELAY;

   

    EP6AUTOINLENL = 0x40;

   

    SYNCDELAY;

   

    EP8AUTOINLENL = 0x40;

   

  }

   

      

   

  Configuration = SETUPDAT[ 2 ];

   

  return( TRUE );        // Handled by user code

   

}

   

 

   

BOOL DR_GetConfiguration( void )   

   

{ // Called when a Get Configuration command is received

   

   EP0BUF[ 0 ] = Configuration;

   

   EP0BCH = 0;

   

   EP0BCL = 1;

   

   return(TRUE);          // Handled by user code

   

}

   

 

   

BOOL DR_SetInterface( void )       

   

{ // Called when a Set Interface command is received

   

   AlternateSetting = SETUPDAT[ 2 ];

   

   return( TRUE );        // Handled by user code

   

}

   

 

   

BOOL DR_GetInterface( void )       

   

{ // Called when a Set Interface command is received

   

   EP0BUF[ 0 ] = AlternateSetting;

   

   EP0BCH = 0;

   

   EP0BCL = 1;

   

   return( TRUE );        // Handled by user code

   

}

   

 

   

BOOL DR_GetStatus( void )

   

{

   

   return( TRUE );

   

}

   

 

   

BOOL DR_ClearFeature( void )

   

{

   

   return( TRUE );

   

}

   

 

   

BOOL DR_SetFeature( void )

   

{

   

   return( TRUE );

   

}

   

 

   

 

   

///////////////////////////////////////////////////////////////////////////////////////////////////////////

   

 

   

/*

   

BOOL DR_VendorCmnd( void )

   

{

   

 

   

 

   

 

   

wValue = SETUPDAT[2];

   

wValue |= SETUPDAT[3]<<8;

   

 

   

wIndex = SETUPDAT[4];

   

wIndex |= SETUPDAT[5]<<8;

   

 

   

 

   

switch (SETUPDAT[1])

   

  {

   

 

   

case VENDOR_CMD1: //LED_ON

   

 

   

EZUSB_InitI2C();

   

Cmd1[0] = SETUPDAT[2];

   

Cmd1[1] = SETUPDAT[4];

   

 

   

 

   

//EZUSB_WriteI2C(wValue, 0x01, Cmd1);

   

// EZUSB_WriteI2C( 0x20 , 0x02, Cmd1);

   

EZUSB_WriteI2C( wValue , 0x01, wIndex);

   

///

   

// EZUSB_WriteI2C(0x20, 0x02, Cmd1);

   

break;

   

 

   

 

   

  case VENDOR_CMD2:

   

EZUSB_InitI2C();

   

 

   

//EZUSB_WriteI2C(wValue, 0x01, Cmd1);

   

// EZUSB_WriteI2C( 0x20 , 0x02, Cmd1);

   

// EZUSB_WriteI2C( 0x20 , 0x01, 0x44);

   

EZUSB_WriteI2C( SETUPDAT[2] , 0x01, SETUPDAT[4]);

   

 

   

   

 

   

EZUSB_ReadI2C(SETUPDAT[2], 0x01, Cmd1 );

   

 

   

EP0BUF[0] = Cmd1[0];

   

EP0BCH = 0;

   

EP0BCL = 1;

   

EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request

   

 

   

 

   

break;

   

 

   

default:

   

   return(TRUE);

   

  }

   

 

   

  return( FALSE );

   

}

   

*/

   

 

   

BOOL DR_VendorCmnd(void)

   

{

   

// WORD addr;//, len;//, bc;

   

// WORD ChipRev;

   

// WORD i;

   

 

   

CPUCS = 0x10;//2;

   

 

   

wValue = SETUPDAT[2];

   

wValue |= SETUPDAT[3]<<8;

   

 

   

wIndex = SETUPDAT[4];

   

wIndex |= SETUPDAT[5]<<8;

   

 

   

 

   

switch(SETUPDAT[1])

   

{ //TPM handle new commands

   

 

   

////////////////////////////////////////////////////////////////////////////////

   

 

   

case VENDOR_CMD1: //LED_ON OEA=0x

   

EZUSB_InitI2C(); // Initialize I2C Bus

   

 

   

   

Cmd1[0] = SETUPDAT[2];

   

Cmd1[1] = SETUPDAT[4];

   

   

   

EZUSB_WriteI2C(0x20, 0x02, Cmd1);

   

 

   

EP0BCH = 0;

   

EP0BCL = 1;

   

EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request OEA OEA = if(S if(SET

   

 

   

break;

   

 

   

 

   

case VENDOR_CMD2:

   

EZUSB_InitI2C(); // Initialize I2C Bus

   

 

   

Cmd3[0] = SETUPDAT[4];

   

 

   

 

   

EZUSB_WriteI2C(0x20, 0x01, Cmd3);

   

 

   

EZUSB_ReadI2C(0x20, 0x01, Cmd3 );

   

 

   

EP0BUF[0] = Cmd3[0];

   

EP0BCH = 0;

   

EP0BCL = 1;

   

EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request

   

 

   

 

   

break;

   

//////////////////////////////////////////////////////////////////////////////

   

 

   

 

   

 

   

 

   

 

   

 

   

 

   

/*

   

case VR_DB_FX:

   

DB_Addr = 0x01; //TPM: need to assert double byte

   

I2C_Addr |= 0x01; //TPM: need to assert double byte

   

      addr = SETUPDAT[2]; // Get address and length

   

addr |= SETUPDAT[3] << 8;

   

len = SETUPDAT[6];

   

len |= SETUPDAT[7] << 8;

   

// Is this an upload command ?

   

if(SETUPDAT[0] == VR_UPLOAD)

   

{

   

while(len) // Move requested data through EP0IN 

   

{ // one packet at a time.

   

 

   

               while(EP0CS & bmEPBUSY);

   

 

   

if(len < EP0BUFF_SIZE)

   

bc = len;

   

else

   

bc = EP0BUFF_SIZE;

   

 

   

for(i=0; i<bc; i++)

   

*(EP0BUF+i) = 0xcd;

   

EEPROMRead(addr,(WORD)bc,(WORD)EP0BUF);

   

 

   

EP0BCH = 0;

   

EP0BCL = (BYTE)bc; // Arm endpoint with # bytes to transfer

   

 

   

addr += bc;

   

len -= bc;

   

}

   

}

   

// Is this a download command ?

   

else if(SETUPDAT[0] == VR_DOWNLOAD)

   

{

   

while(len) // Move new data through EP0OUT 

   

{ // one packet at a time.

   

// Arm endpoint - do it here to clear (after sud avail)

   

EP0BCH = 0;

   

EP0BCL = 0; // Clear bytecount to allow new data in; also stops NAKing

   

 

   

while(EP0CS & bmEPBUSY);

   

 

   

bc = EP0BCL; // Get the new bytecount

   

 

   

EEPROMWrite(addr,bc,(WORD)EP0BUF);

   

 

   

addr += bc;

   

len -= bc;

   

}

   

}

   

   

break;

   

   

case VR_RAM:

   

 // NOTE: This case falls through !

   

case VR_EEPROM:

   

DB_Addr = 0x00; //TPM: need to assert double byte

   

I2C_Addr |= 0x00; //TPM: need to assert double byte

   

addr = SETUPDAT[2]; // Get address and length

   

addr |= SETUPDAT[3] << 8;

   

len = SETUPDAT[6];

   

len |= SETUPDAT[7] << 8;

   

// Is this an upload command ?

   

if(SETUPDAT[0] == VR_UPLOAD)

   

{

   

while(len) // Move requested data through EP0IN 

   

{ // one packet at a time.

   

 

   

               while(EP0CS & bmEPBUSY);

   

 

   

if(len < EP0BUFF_SIZE)

   

bc = len;

   

else

   

bc = EP0BUFF_SIZE;

   

 

   

// Is this a RAM upload ?

   

if(SETUPDAT[1] == VR_RAM)

   

{

   

for(i=0; i<bc; i++)

   

*(EP0BUF+i) = *((BYTE xdata *)addr+i);

   

}

   

else

   

{

   

for(i=0; i<bc; i++)

   

*(EP0BUF+i) = 0xcd;

   

EEPROMRead(addr,(WORD)bc,(WORD)EP0BUF);

   

}

   

 

   

EP0BCH = 0;

   

EP0BCL = (BYTE)bc; // Arm endpoint with # bytes to transfer

   

 

   

addr += bc;

   

len -= bc;

   

 

   

}

   

}

   

// Is this a download command ?

   

else if(SETUPDAT[0] == VR_DOWNLOAD)

   

{

   

while(len) // Move new data through EP0OUT 

   

{ // one packet at a time.

   

// Arm endpoint - do it here to clear (after sud avail)

   

EP0BCH = 0;

   

EP0BCL = 0; // Clear bytecount to allow new data in; also stops NAKing

   

 

   

while(EP0CS & bmEPBUSY);

   

 

   

bc = EP0BCL; // Get the new bytecount

   

 

   

// Is this a RAM download ?

   

if(SETUPDAT[1] == VR_RAM)

   

{

   

for(i=0; i<bc; i++)

   

*((BYTE xdata *)addr+i) = *(EP0BUF+i);

   

}

   

else

   

EEPROMWrite(addr,bc,(WORD)EP0BUF);

   

 

   

addr += bc;

   

len -= bc;

   

}

   

}

   

break;

   

*/

   

}

   

return(FALSE); // no error; command handled OK

   

}

   

 

   

//-----------------------------------------------------------------------------

   

// USB Interrupt Handlers

   

//   The following functions are called by the USB interrupt jump table.

   

//-----------------------------------------------------------------------------

   

 

   

// Setup Data Available Interrupt Handler

   

void ISR_Sudav( void ) interrupt 0

   

{

   

   GotSUD = TRUE;         // Set flag

   

   EZUSB_IRQ_CLEAR( );

   

   USBIRQ = bmSUDAV;      // Clear SUDAV IRQ

   

}

   

 

   

// Setup Token Interrupt Handler

   

void ISR_Sutok( void ) interrupt 0

   

{

   

   EZUSB_IRQ_CLEAR( );

   

   USBIRQ = bmSUTOK;      // Clear SUTOK IRQ

   

}

   

 

   

void ISR_Sof( void ) interrupt 0

   

{

   

   EZUSB_IRQ_CLEAR( );

   

   USBIRQ = bmSOF;        // Clear SOF IRQ

   

}

   

 

   

void ISR_Ures( void ) interrupt 0

   

{

   

   if ( EZUSB_HIGHSPEED( ) )

   

   {

   

      pConfigDscr = pHighSpeedConfigDscr;

   

      pOtherConfigDscr = pFullSpeedConfigDscr;

   

   }

   

   else

   

   {

   

      pConfigDscr = pFullSpeedConfigDscr;

   

      pOtherConfigDscr = pHighSpeedConfigDscr;

   

   }

   

   

   

   EZUSB_IRQ_CLEAR( );

   

   USBIRQ = bmURES;       // Clear URES IRQ

   

}

   

 

   

void ISR_Susp( void ) interrupt 0

   

{

   

   Sleep = TRUE;

   

   EZUSB_IRQ_CLEAR( );

   

   USBIRQ = bmSUSP;

   

}

   

 

   

void ISR_Highspeed( void ) interrupt 0

   

{

   

   if ( EZUSB_HIGHSPEED( ) )

   

   {

   

      pConfigDscr = pHighSpeedConfigDscr;

   

      pOtherConfigDscr = pFullSpeedConfigDscr;

   

   }

   

   else

   

   {

   

      pConfigDscr = pFullSpeedConfigDscr;

   

      pOtherConfigDscr = pHighSpeedConfigDscr;

   

   }

   

 

   

   EZUSB_IRQ_CLEAR( );

   

   USBIRQ = bmHSGRANT;

   

}

   

void ISR_Ep0ack( void ) interrupt 0

   

{

   

}

   

void ISR_Stub( void ) interrupt 0

   

{

   

}

   

void ISR_Ep0in( void ) interrupt 0

   

{

   

}

   

void ISR_Ep0out( void ) interrupt 0

   

{

   

}

   

void ISR_Ep1in( void ) interrupt 0

   

{

   

}

   

void ISR_Ep1out( void ) interrupt 0

   

{

   

}

   

void ISR_Ep2inout( void ) interrupt 0

   

{

   

}

   

void ISR_Ep4inout( void ) interrupt 0

   

{

   

}

   

void ISR_Ep6inout( void ) interrupt 0

   

{

   

}

   

void ISR_Ep8inout( void ) interrupt 0

   

{

   

}

   

void ISR_Ibn( void ) interrupt 0

   

{

   

}

   

void ISR_Ep0pingnak( void ) interrupt 0

   

{

   

}

   

void ISR_Ep1pingnak( void ) interrupt 0

   

{

   

}

   

void ISR_Ep2pingnak( void ) interrupt 0

   

{

   

}

   

void ISR_Ep4pingnak( void ) interrupt 0

   

{

   

}

   

void ISR_Ep6pingnak( void ) interrupt 0

   

{

   

}

   

void ISR_Ep8pingnak( void ) interrupt 0

   

{

   

}

   

void ISR_Errorlimit( void ) interrupt 0

   

{

   

}

   

void ISR_Ep2piderror( void ) interrupt 0

   

{

   

}

   

void ISR_Ep4piderror( void ) interrupt 0

   

{

   

}

   

void ISR_Ep6piderror( void ) interrupt 0

   

{

   

}

   

void ISR_Ep8piderror( void ) interrupt 0

   

{

   

}

   

void ISR_Ep2pflag( void ) interrupt 0

   

{

   

}

   

void ISR_Ep4pflag( void ) interrupt 0

   

{

   

}

   

void ISR_Ep6pflag( void ) interrupt 0

   

{

   

}

   

void ISR_Ep8pflag( void ) interrupt 0

   

{

   

}

   

void ISR_Ep2eflag( void ) interrupt 0

   

{

   

}

   

void ISR_Ep4eflag( void ) interrupt 0

   

{

   

}

   

void ISR_Ep6eflag( void ) interrupt 0

   

{

   

}

   

void ISR_Ep8eflag( void ) interrupt 0

   

{

   

}

   

void ISR_Ep2fflag( void ) interrupt 0

   

{

   

}

   

void ISR_Ep4fflag( void ) interrupt 0

   

{

   

}

   

void ISR_Ep6fflag( void ) interrupt 0

   

{

   

}

   

void ISR_Ep8fflag( void ) interrupt 0

   

{

   

}

   

void ISR_GpifComplete( void ) interrupt 0

   

{

   

}

   

void ISR_GpifWaveform( void ) interrupt 0

   

{

   

}

   

 

   

// ...debug LEDs: accessed via movx reads only ( through CPLD )

   

// it may be worth noting here that the default monitor loads at 0xC000

   

 

   

// use this global variable when (de)asserting debug LEDs...

   

/*

   

void EEPROMWriteByte(WORD addr, BYTE value)

   

{

   

BYTE i = 0;

   

BYTE xdata ee_str[3];

   

 

   

if(DB_Addr)

   

ee_str[i++] = MSB(addr);

   

 

   

ee_str[i++] = LSB(addr);

   

ee_str[i++] = value;

   

 

   

EZUSB_WriteI2C(I2C_Addr, i, ee_str);

   

   EZUSB_WaitForEEPROMWrite(I2C_Addr);

   

}

   

 

   

 

   

void EEPROMWrite(WORD addr, BYTE length, BYTE xdata *buf)

   

{

   

BYTE i;

   

for(i=0;i<length;++i)

   

EEPROMWriteByte(addr++,buf);

   

}

   

 

   

void EEPROMRead(WORD addr, BYTE length, BYTE xdata *buf)

   

{

   

BYTE i = 0;

   

BYTE j = 0;

   

BYTE xdata ee_str[2];

   

 

   

if(DB_Addr)

   

ee_str[i++] = MSB(addr);

   

 

   

ee_str[i++] = LSB(addr);

   

 

   

EZUSB_WriteI2C(I2C_Addr, i, ee_str);

   

 

   

// for(j=0; j < length; j++)

   

// *(buf+j) = 0xcd;

   

 

   

EZUSB_ReadI2C(I2C_Addr, length, buf);

   

}

   

*/

   
        
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