We developted FPGA based emulator. We will use probably a FX2LP18 to configure the FPGA (GPIF mode) and after configuration done, in SlaveFIFO mode to communicate with HOST PC (and exchange DATA between FPGA and PC).
Normally, the HOST PC is the master, it asks for getting DATA in the FPGA trough the FX2.
Is there any possibility to make the FPGA "master". I.e is the FPGA can inform by itself the FX2 that is has DATA to send ? (using the WAKEUP for instance or any FX2 PIN to manage an interrupt).