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USB Low-Full-High Speed Peripherals

JeBo_4132831
Contributor

Hi,

We developted FPGA based emulator. We will use probably a FX2LP18 to configure the FPGA (GPIF mode) and after configuration done, in SlaveFIFO mode to communicate with HOST PC (and exchange DATA between FPGA and PC).

Normally, the HOST PC is the master, it asks for getting DATA in the FPGA trough the FX2.

Is there any possibility to make the FPGA "master". I.e is the FPGA can inform by itself the FX2 that is has DATA to send ? (using the WAKEUP for instance or any FX2 PIN to manage an interrupt).

Regards

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1 Solution
YatheeshD_36
Moderator
Moderator

Hello,

Yes, the FX2LP configured as a FIFO Slave can indicate the master (FPGA in your case) that it has data to send using the FIFO Status Flags. 

For an example please refer to the application note AN61345 Designing with EZ-USB® FX2LP™ Slave FIFO Interface​ where FLAG A is used to indicate the empty status of EP2 OUT FIFO and FLAG D is used to indicate the full status of EP6 IN FIFO, to the FPGA.

The EZ-USB Technical Reference manual contains more details on the Flag usage. Refer to section 9.2.4 in the manual.

Thanks,

Yatheesh

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YatheeshD_36
Moderator
Moderator

Hello,

Yes, the FX2LP configured as a FIFO Slave can indicate the master (FPGA in your case) that it has data to send using the FIFO Status Flags. 

For an example please refer to the application note AN61345 Designing with EZ-USB® FX2LP™ Slave FIFO Interface​ where FLAG A is used to indicate the empty status of EP2 OUT FIFO and FLAG D is used to indicate the full status of EP6 IN FIFO, to the FPGA.

The EZ-USB Technical Reference manual contains more details on the Flag usage. Refer to section 9.2.4 in the manual.

Thanks,

Yatheesh

View solution in original post

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