I see that this forum is not used often and most questions are not even commented at all. Anyway this is what I found out yesterday. I'm using GPIF master mode to send and receive data to and from the periferal using 2 TI fifos both connected to the FD pins.
I've been working with the reading through gpif. I noted that the data received didn't match the data sent from the periferal. Also that every bulk transaction the external fifo would be emptied no matter how many words were read.
Finally I decided to go and buy a cheap logic analyzer to see what was going on since I couldn't check with my oscilloscope. I got the Techtools DV3100. It was very easy to configure and use. So I connected it to my dev board and run a test. I was using basically the single read wave form from the gpif primer setting. I found that in S0 the REN signal would stay low for a LOT of ifclks and in S1 REN goes high and OE low to perform the read. The OE is correct with one clock wide only, but obviously the external data has depleted. I just couldn't make GPIF designer to make S0 to last only 1 clock so I ignored S0 and shifted everything one clock. son S0 now is S1 ans so on. I'm wasting a clock, but in S1 and S2 everything works fine.
I checked that S0 was 1 clock long, but somehow whenever I trigger the waveform is stays in S0 for a long time.
Also I found that the Ifclk is not in sync all the time if you run it at 48mhz, I found that at 30mhz runs much stable. I observed this behavior with my new logic analyzer ($500) from digikey.