I'm trying to use the synchronous Slave FIFO from the FPGA.
FX2LP configuration is as follows:
EP2 - AUTOIN 16bit 1k * 3x buff.
EP8 - AUTOOUT 16bit 512b * 2x buff.
I am sending data through CyConsole. The packet in EP8 - sent without errors (more than two packet). This means that the FIFO is emptied regularly (SLOE and SLRD - active, FIFOADDR = 11, SLCS # - not used). FlagB is configured as "empty fifo". When sending a packet - flagB changes. The packet comes in a FIFO. Then the FIFO is emptied again and FlagB changes again.
However, I do not see any data sent on the bus FD [0-15].
Instead, the bus exhibited values 0xFFFF.
how to explain this situation???
P.S. FD [0-15] bus - working. I configured it as an IO-port and saw the correct values on the chip legs FX2LP....