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hello!
I'm trying to use the synchronous Slave FIFO from the FPGA.
FX2LP configuration is as follows:
EP2 - AUTOIN 16bit 1k * 3x buff.
EP8 - AUTOOUT 16bit 512b * 2x buff.
I am sending data through CyConsole. The packet in EP8 - sent without errors (more than two packet). This means that the FIFO is emptied regularly (SLOE and SLRD - active, FIFOADDR = 11, SLCS # - not used). FlagB is configured as "empty fifo". When sending a packet - flagB changes. The packet comes in a FIFO. Then the FIFO is emptied again and FlagB changes again.
However, I do not see any data sent on the bus FD [0-15].
Instead, the bus exhibited values 0xFFFF.
how to explain this situation???
P.S. FD [0-15] bus - working. I configured it as an IO-port and saw the correct values on the chip legs FX2LP....
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described configuration - running!!!
......After dancing with a tambourine.
EP2CFG = bmEP_CFG_ACTIVE | bmEP_CFG_IN | bmEP_CFG_BUILK | bmEP_CFG_1K | bmEP_CFG_BUFx3;
SYNCDELAY;
EP4CFG = (EP4CFG & 0x7F);
SYNCDELAY;
EP6CFG = bmEP_CFG_ACTIVE | bmEP_CFG_IN | bmEP_CFG_BUILK | bmEP_CFG_512 | bmEP_CFG_BUFx3 ;
SYNCDELAY;
EP6CFG = (EP6CFG & 0x7F);//--------------reset EP_CFG_ACTIVE only after set.
SYNCDELAY;
EP8CFG = bmEP_CFG_ACTIVE | bmEP_CFG_OUT| bmEP_CFG_BUILK;
SYNCDELAY;
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Thanks for updating!