cancel
Showing results for 
Search instead for 
Did you mean: 

USB Low-Full-High Speed Peripherals

Anonymous
Not applicable

Hello.

I am developing a product using the CY7C68013A-56 chip.

I am working on connecting the Altera FPGA chip to the CY7C68013 chip and
sending the data to the PC.

I set the Slave FIFO mode by referring to the Cypress AN61345 example and
created the 8051 firmware.

Driver installation and loading, basic operation is completed.

However, when data is written to the FIFO by setting the slwr signal to Low
level in the
FPGA The driver resets and does not load normally.


If you delete the part that makes the slwr signal low level, the USB driver
normally It works.

The problem that the USB driver is reset when the slwr signal is set

to low level has not been solved.

Thank you.

0 Likes
1 Solution
SrinathS_16
Moderator
Moderator

Hello Sanggyu Park,

The driver version that you have mentioned is an older one. Kindly, modify the driver to CYUSB3.SYS which can be obtained from the below link.

http://www.cypress.com/file/322371

Also, you have mentioned that the driver is reset when the SLWR signal is asserted. Can you please let me know what you mean by driver getting reset?

Best regards,

Srinath S

View solution in original post

4 Replies
SrinathS_16
Moderator
Moderator

Hello Sanggyu Park,

- Can you please post the code snippet of the firmware in the TD_POLL() block?

- Also, please let me know the driver version and the OS that you are using.

- In case you have modified the fw.c file in the firmware, please mention the same.

Best regards,

Srinath S

Anonymous
Not applicable

Hello Srinath S

Thank you for answering my question.

The TD_Poll () block is shown in bold.

The fw.c file has no modifications.

OS : Windows 7 64bit

Driver :  CySuiteUSB_3_4_7_B204 

Best regards,

Sang-gyu, Park.

#pragma NOIV                    // Do not generate interrupt vectors

//-----------------------------------------------------------------------------
//   File:      slave.c
//   Contents:  Hooks required to implement USB peripheral function.
//              Code written for FX2 REVE 56-pin and above.
//              This firmware is used to demonstrate FX2 Slave FIF
//              operation.
//              operation.
//   Copyright (c) 2003 Cypress Semiconductor All rights reserved
//-----------------------------------------------------------------------------
#include "fx2.h"
#include "fx2regs.h"
#include "fx2sdly.h"            // SYNCDELAY macro

extern BOOL GotSUD;             // Received setup data flag
extern BOOL Sleep;
extern BOOL Rwuen;
extern BOOL Selfpwr;

BYTE Configuration;             // Current configuration
BYTE AlternateSetting;          // Alternate settings

BOOL g_Done_frm_fpga = FALSE;

BOOL g_bTDPollInit = FALSE;
int g_nLoopCnt = 0;
BOOL g_bLedFlag = FALSE;
BOOL g_bIfconfigSetDone = FALSE;

void TD_Init(void)
{
// Called once at startup
long i = 0;

CPUCS = 0x12;      // CLKSPD[4:3]=10, for 48MHz operation, [b1:1]output CLKOUT, [b0:0]8051 Run
SYNCDELAY;

//-----------------------------------------------------------
PINFLAGSAB = 0x08;    // FLAGA - EP2 EF
SYNCDELAY;

PINFLAGSCD = 0xE0;    // FLAGD - EP6 FF
SYNCDELAY;

//-----------------------------------------------------------
PORTACFG |= 0x80;    // b7:FLAGD
SYNCDELAY;

//-----------------------------------------------------------
IFCONFIG = 0xE3;     // Internal clock, 48 MHz, Pin Drive, Sync, Slave FIFO interface
SYNCDELAY;

// REVCTL = 0x03;
// SYNCDELAY;

//-----------------------------------------------------------
EP2CFG = 0xA0;                 // out 512 bytes, 4x, bulk
SYNCDELAY;                   

EP6CFG = 0xE0;                 // in 512 bytes, 4x, bulk
SYNCDELAY;             

EP4CFG = 0x02;                 //
SYNCDELAY;                    

EP8CFG = 0x02;                 //
SYNCDELAY;

FIFORESET = 0x80;              // activate NAK-ALL to avoid race conditions
SYNCDELAY;                     // see TRM section 15.14

FIFORESET = 0x02;              // reset, FIFO 2
SYNCDELAY;                     //

FIFORESET = 0x04;              // reset, FIFO 4
SYNCDELAY;                     //

FIFORESET = 0x06;              // reset, FIFO 6
SYNCDELAY;                     //

FIFORESET = 0x08;              // reset, FIFO 8
SYNCDELAY;                     //

FIFORESET = 0x00;              // deactivate NAK-ALL
SYNCDELAY;                     //

EP2FIFOCFG = 0x00;             // AUTOOUT=0, WORDWIDE=1
SYNCDELAY;                     //
 
// core needs to see AUTOOUT=0 to AUTOOUT=1 switch to arm endp's
EP2FIFOCFG = 0x11;             // AUTOOUT=1, WORDWIDE=1
SYNCDELAY;                     //

// EP4FIFOCFG = 0x11;             // AUTOOUT=1, WORDWIDE=1
// SYNCDELAY;                     //

EP6FIFOCFG = 0x0D;             // AUTOIN=1, ZEROLENIN=1, WORDWIDE=1
SYNCDELAY;                     //

// EP8FIFOCFG = 0x0D;             // AUTOIN=1, ZEROLENIN=1, WORDWIDE=1
// SYNCDELAY;                     //

//-----------------------------------------------------------
OEA &= ~(1 << 0);     // Declare PA.0 Input
SYNCDELAY;

OEA |= (1 << 1);    // Declare PA.1 Output
SYNCDELAY;

OEA |= (1 << 3);    // Declare PA.3 Output
SYNCDELAY;

IOA |= (1 << 1);    // PA.1 <= '1'; 
SYNCDELAY;

}

void TD_Poll(void)
{
   // Called repeatedly while the device is idle

  if((!g_Done_frm_fpga) && (IOA & 0x01))              // PA.0(IOA.0)  <-  In from FPGA  [FPGA USB process Ready]
  {
      IFCONFIG = 0x43;          // External clock input, Slave FIFO interface
      SYNCDELAY;

      IOA &= ~(1 << 1);           // PA.1 <= '0';   ->  Out to FPGA [FPGA USB process Run]
     SYNCDELAY;
 
    g_Done_frm_fpga = TRUE;
    g_bIfconfigSetDone = TRUE;
}

//----------------------------------------------------------------------
if(g_bIfconfigSetDone)
{
  if(g_nLoopCnt > 10000)
  {
   if(!g_bLedFlag)
   {
    IOA &= ~(1 << 3);
    SYNCDELAY;

    g_bLedFlag = 1;
   }
   else
   {
    IOA |= (1 << 3);
    SYNCDELAY;
   
    g_bLedFlag = 0;
   }
   g_nLoopCnt = 0;
  }
  g_nLoopCnt ++;
}
}

BOOL TD_Suspend( void )         
{ // Called before the device goes into suspend mode
return( TRUE );
}

BOOL TD_Resume( void )         
{ // Called after the device resumes
return( TRUE );
}

//-----------------------------------------------------------------------------
// Device Request hooks
//   The following hooks are called by the end point 0 device request parser.
//-----------------------------------------------------------------------------
BOOL DR_GetDescriptor( void )
{
return( TRUE );
}

BOOL DR_SetConfiguration( void )  
{ // Called when a Set Configuration command is received
if(EZUSB_HIGHSPEED())
{ // ...FX2 in high speed mode
  EP6AUTOINLENH = 0x02;
  SYNCDELAY;
   
  EP8AUTOINLENH = 0x02;   // set core AUTO commit len = 512 bytes
  SYNCDELAY;
   
  EP6AUTOINLENL = 0x00;
  SYNCDELAY;

  EP8AUTOINLENL = 0x00;
  SYNCDELAY;
}
else
{ // ...FX2 in full speed mode
  EP6AUTOINLENH = 0x00;
  SYNCDELAY;
   
  EP8AUTOINLENH = 0x00;   // set core AUTO commit len = 64 bytes
  SYNCDELAY;
   
  EP6AUTOINLENL = 0x40;
  SYNCDELAY;
   
  EP8AUTOINLENL = 0x40;
  SYNCDELAY;
}
     
Configuration = SETUPDAT[2];

return(TRUE);        // Handled by user code
}

BOOL DR_GetConfiguration( void )  
{ // Called when a Get Configuration command is received
EP0BUF[0] = Configuration;
EP0BCH = 0;
EP0BCL = 1;
  
return(TRUE);          // Handled by user code
}

BOOL DR_SetInterface( void )      
{ // Called when a Set Interface command is received
AlternateSetting = SETUPDAT[2];
  
return( TRUE );        // Handled by user code
}

BOOL DR_GetInterface( void )      
{ // Called when a Set Interface command is received
EP0BUF[0] = AlternateSetting;
EP0BCH = 0;
EP0BCL = 1;
  
return( TRUE );        // Handled by user code
}

BOOL DR_GetStatus( void )
{
return( TRUE );
}

BOOL DR_ClearFeature( void )
{
return( TRUE );
}

BOOL DR_SetFeature( void )
{
return( TRUE );
}

BOOL DR_VendorCmnd( void )
{
return( TRUE );
}

//-----------------------------------------------------------------------------
// USB Interrupt Handlers
//   The following functions are called by the USB interrupt jump table.
//-----------------------------------------------------------------------------
// Setup Data Available Interrupt Handler
void ISR_Sudav( void ) interrupt 0
{
GotSUD = TRUE;         // Set flag
EZUSB_IRQ_CLEAR( );
USBIRQ = bmSUDAV;      // Clear SUDAV IRQ
}

// Setup Token Interrupt Handler
void ISR_Sutok( void ) interrupt 0
{
EZUSB_IRQ_CLEAR( );
USBIRQ = bmSUTOK;      // Clear SUTOK IRQ
}

void ISR_Sof( void ) interrupt 0
{
EZUSB_IRQ_CLEAR( );
USBIRQ = bmSOF;        // Clear SOF IRQ
}

void ISR_Ures( void ) interrupt 0
{
if ( EZUSB_HIGHSPEED( ) )
{
  pConfigDscr = pHighSpeedConfigDscr;
  pOtherConfigDscr = pFullSpeedConfigDscr;
}
else
{
  pConfigDscr = pFullSpeedConfigDscr;
  pOtherConfigDscr = pHighSpeedConfigDscr;
}
  
EZUSB_IRQ_CLEAR( );
USBIRQ = bmURES;       // Clear URES IRQ
}

void ISR_Susp( void ) interrupt 0
{
Sleep = TRUE;
EZUSB_IRQ_CLEAR( );
USBIRQ = bmSUSP;
}

void ISR_Highspeed( void ) interrupt 0
{
if(EZUSB_HIGHSPEED())
{
  pConfigDscr = pHighSpeedConfigDscr;
  pOtherConfigDscr = pFullSpeedConfigDscr;
}
else
{
  pConfigDscr = pFullSpeedConfigDscr;
  pOtherConfigDscr = pHighSpeedConfigDscr;
}

EZUSB_IRQ_CLEAR();
USBIRQ = bmHSGRANT;
}

void ISR_Ep0ack( void ) interrupt 0
{
}

void ISR_Stub( void ) interrupt 0
{
}

void ISR_Ep0in( void ) interrupt 0
{
}

void ISR_Ep0out( void ) interrupt 0
{
}

void ISR_Ep1in( void ) interrupt 0
{
}

void ISR_Ep1out( void ) interrupt 0
{
}

void ISR_Ep2inout( void ) interrupt 0
{
}

void ISR_Ep4inout( void ) interrupt 0
{
}

void ISR_Ep6inout( void ) interrupt 0
{
}

void ISR_Ep8inout( void ) interrupt 0
{
}

void ISR_Ibn( void ) interrupt 0
{
}

void ISR_Ep0pingnak( void ) interrupt 0
{
}

void ISR_Ep1pingnak( void ) interrupt 0
{
}

void ISR_Ep2pingnak( void ) interrupt 0
{
}

void ISR_Ep4pingnak( void ) interrupt 0
{
}

void ISR_Ep6pingnak( void ) interrupt 0
{
}

void ISR_Ep8pingnak( void ) interrupt 0
{
}

void ISR_Errorlimit( void ) interrupt 0
{
}

void ISR_Ep2piderror( void ) interrupt 0
{
}

void ISR_Ep4piderror( void ) interrupt 0
{
}

void ISR_Ep6piderror( void ) interrupt 0
{
}

void ISR_Ep8piderror( void ) interrupt 0
{
}

void ISR_Ep2pflag( void ) interrupt 0
{
}

void ISR_Ep4pflag( void ) interrupt 0
{
}

void ISR_Ep6pflag( void ) interrupt 0
{
}

void ISR_Ep8pflag( void ) interrupt 0
{
}

void ISR_Ep2eflag( void ) interrupt 0
{
}

void ISR_Ep4eflag( void ) interrupt 0
{
}

void ISR_Ep6eflag( void ) interrupt 0
{
}

void ISR_Ep8eflag( void ) interrupt 0
{
}

void ISR_Ep2fflag( void ) interrupt 0
{
}

void ISR_Ep4fflag( void ) interrupt 0
{
}

void ISR_Ep6fflag( void ) interrupt 0
{
}

void ISR_Ep8fflag( void ) interrupt 0
{
}

void ISR_GpifComplete( void ) interrupt 0
{
}

void ISR_GpifWaveform( void ) interrupt 0
{
}

0 Likes
SrinathS_16
Moderator
Moderator

Hello Sanggyu Park,

The driver version that you have mentioned is an older one. Kindly, modify the driver to CYUSB3.SYS which can be obtained from the below link.

http://www.cypress.com/file/322371

Also, you have mentioned that the driver is reset when the SLWR signal is asserted. Can you please let me know what you mean by driver getting reset?

Best regards,

Srinath S

View solution in original post

Anonymous
Not applicable

Hello Srinath S

Thank you for answering my question.

If the slwr signal is set to low level in Slave FIFO mode, the driver will not be loaded.

Keeping the slwr signal high keeps the driver in normal condition.

I tried changing it to the driver you provided, but it is the same.

If the slwr signal is set to low level in the default state("Cypress EZ-USB FX2LP No EEPROM")

in which the firmware is not loaded, driver recognition will fail.

I tried the internal clock and the external clock, but the symptoms are the same.

It is not solved for several days. Help me...

Best regards,

Sang-gyu, Park.

0 Likes