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USB Low-Full-High Speed Peripherals

hiyac_351831
New Contributor II

I checked document, #001-13670 EZ-USB Technical Reference Manual.
http://www.cypress.com/file/126446/download

I am question about Figure 9-1 at see page 99.

Question:
Could you tell me FPGA can read data from the CPU EP0?
I understand for readable EPx is EP2, EP4, EP6, EP8.

Best Regards.

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1 Solution
SrinathS_16
Moderator
Moderator

Hello Hiroki Yamashita-san,

Generally, the FPGA gets interfaced to the FX2LP over the slave FIFO interface. Under this situation, only the endpoints EP2, EP4, EP6, EP8 are accessible by the FPGA.

Best regards,

Srinath S

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SrinathS_16
Moderator
Moderator

Hello Hiroki Yamashita-san,

Generally, the FPGA gets interfaced to the FX2LP over the slave FIFO interface. Under this situation, only the endpoints EP2, EP4, EP6, EP8 are accessible by the FPGA.

Best regards,

Srinath S

View solution in original post

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