USB EZ-PD™ Type-C Forum Discussions
Hello
I would like to detect the connection/disconnection status with the HOST device and output a (GPIO) signal to the external EC.
In details, Specifically, when the PDO contract is made, the BCR notifies the external EC with a GPIO signal (Hi or Lo)
When the host is disconnected, the BCR notifies the external EC with a GPIO signal (Hi or Lo)
Q1) Is it possible to use BCR to output the above detection signal to an external EC via GPIO, etc.? Which pin can I use if possible?
Q2) Tell me about the usage of "Pin 8 GPIO_1". Is it possible to use the above detection signal?
Best Regards
Show LessCould you share me a link that is project FW based on CCG4?
please help check the follow problems:
1、When we test 5V/3A, 9V/2A,the OCP trigger is below:
a、Expect test results:
5V/3A: 3A * (1 +10%) = 3.3 A , gain_sel : 0x16 , vref_sel : 62 ---->Vsense : 1.92*2 = 3.84V (above 10%?why)
9V/2A: 2A * (1 +10%) = 2.22A, gain_sel : 0x1B , vref_sel : 55 --->Vsense : 1.85*2 = 2.7v(above 10%?why)
b、Actual test results : whether OCP trigger threshold is OK? 10% thresold?
5V/3A:about 3.7-3.8 A
9V/2A: about 2.6 A
2、but when we test 15V/2.33A 、15V/3A, it is falied,the actual test results is small than expect value
a、Expect test results:
15V/2.33A :2.33A * (1 +10%)= 2.56 A , gain_sel : 0x16 , vref_sel : 15 -->Vsense : 1.45*2 = 2.9V (above 10%,why?)
15V/3A : 3A * (1 +10%)= 3.3 A , gain_sel : 0x16 , vref_sel : 62 --->Vsense : 1.92*2 = 3.84V (above 10% ,why?)
b、Actual test results : OCP trigger threshold is failed according to expect value above
15V/2.33A :about 1.7 A
15V/3A : about 2.2 A (but 5V/3A is OK)
Show Less
1. Does "VBAT to GND protection" and "VBUS OCP" use the same - resistor current sensor to detect current ? ( pin#18 and pin#19)
2. Application note : This resistor senses the current, and if it exceeds the firmware-configured threshold, the NFET is
turned off to interrupt the current. This protects against over-current conditions caused by external faults
How to set "VBAT to GND" firmware-configured threshold to different value ?
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SDK version: ezpdhostsdk_3.4.0_Windows_x86-x64.exe
....
.\CortexM0\ARM_GCC_541\Debug\hal_ccgx.o .\CortexM0\ARM_GCC_541\Debug\pdss_mx_hal.o .\CortexM0\ARM_GCC_541\Debug\cyfitter_cfg.o .\CortexM0\ARM_GCC_541\Debug\cybootloader.o .\CortexM0\ARM_GCC_541\Debug\cymetadata.o .\CortexM0\ARM_GCC_541\Debug\Cm0Start.o .\CortexM0\ARM_GCC_541\Debug\CYPD5225-96BZXI_notebook.a -mcpu=cortex-m0 -mthumb -l ccgx_hpi_ucsi -l ccgx_pd3 -L Generated_Source\PSoC4 -L .\lib\ccg5_dualport -Wl,-Map,.\CortexM0\ARM_GCC_541\Debug/CYPD5225-96BZXI_notebook.map -T .\cm0gcc.ld -specs=nano.specs -Wl,--gc-sections -flto -Os -g -ffunction-sections -finline-functions -Os -flto -ffat-lto-objects -Wl,--end-group
ERROR: address 0x20240 of G:\temp\CYPD5225-96BZXI_notebook\CYPD5225-96BZXI_notebook.cydsn\CortexM0\ARM_GCC_541\Debug\CYPD5225-96BZXI_notebook.elf section `.text' is not within region `rom'
ERROR: G:\temp\CYPD5225-96BZXI_notebook\CYPD5225-96BZXI_notebook.cydsn\CortexM0\ARM_GCC_541\Debug\CYPD5225-96BZXI_notebook.elf section `.eh_frame' will not fit in region `rom'
ERROR: address 0x20240 of G:\temp\CYPD5225-96BZXI_notebook\CYPD5225-96BZXI_notebook.cydsn\CortexM0\ARM_GCC_541\Debug\CYPD5225-96BZXI_notebook.elf section `.text' is not within region `rom'
ERROR: address 0x20240 of G:\temp\CYPD5225-96BZXI_notebook\CYPD5225-96BZXI_notebook.cydsn\CortexM0\ARM_GCC_541\Debug\CYPD5225-96BZXI_notebook.elf section `.text' is not within region `rom'
ERROR: Firmware binary overlaps with metadata
ERROR: section .cyloadablemeta loaded at [0001fec0,0001feff] overlaps section .text loaded at [0000c400,0002023f]
ERROR: region `rom' overflowed by -256 bytes
collect2.exe: error: ld returned 1 exit status
The command 'arm-none-eabi-gcc.exe' failed with exit code '1'.
Hi ,
I have a question about CCG5 source Vbus OCP。When ocp_cur is 3A,only 3.8A above can trigger OCP .
Normally,3.3A can trigger ,but not function well.(3.3 = 3+10% *3);
What can we do to modify this problem ?
BR
Venus
Show LessHello
https://community.infineon.com/t5/USB-EZ-PD-Type-C/about-the-PMG1-S3-power-supply-for-Vsys-Vbus-c-p0-Vbus-c-p1/ m-p/367578#M7177
Regarding the above link currently being asked, I understood the following answer about the priority of Vbus_c_p0 and Vbus_c_p1 of PMG1-S3.
>The one which is present first will be used by the internal LDO to generate VDDD.
Q) As an additional question, regarding the above priority, is it possible to intentionally change the priority of Vbus_c_p0 and Vbus_c_p1? If possible please let me know how to change it.
Best Regards
Arai
Show LessHi All,
When CYPD5225 enters deep sleep mode ,it keeps this mode only for 3 seconds ( current:800 uA) and then restart(current:8mA)。
Q1:Why does it keep deep sleep mode only for 3 seconds and then restart?
Q2:Entering sleep mode , current is 800 uA, is it right? If not, what is the appropriate value?
Log as follows.
BR
Venus
Show LessHello
I am referring to the PMG1-S3 datasheet 002-31288 Rev. *G, and Figure 10 PMG1-S3 power system block diagram shows three types of power supply for PMG1-S3 (Vsys/Vbus_c_p0/Vbus_c_p1).
Q)
What are the priorities in each case for these power supplies below?
CASE1: If Vsys/Vbus_c_p0/Vbus_c_p1 are all valid, is it correct to assume that Vsys has priority?
CASE2: When Vsys is absent and both Vbus_c_p0/Vbus_c_p1 are valid, what is the condition for determining priority?
ex1) Will the one with the higher voltage have priority?
ex2) how to determine the priority when Vbus_c_p0 and Vbus_c_p1 have the same voltage?
Best Regards
Arai
Show Less
We implement PPS sink on CCG5,follow by Solved: PPS Request for specific Voltage - Infineon Developer Community
1.The function hpi_set_userdef_write_handler (hpi_user_reg_handler) does not work.hpi_user_reg_handler call back function can not be triggered.
2.we don't find APP_PPS_SINK_SUPPORT macro
Show Less