USB EZ-PD™ Type-C Forum Discussions

Attempting to run examples for CCG4 components results in linker failures.

Advice on community has been to use PSoC Creator 3.x.

When will a fix for these issues be available?

Reference:

• "lto-wrapper failed" Error when compiling CCG4 eval board firmware on PSoc 4.2 @ https://community.cypress.com/message/193060
• How to resolve the build error "lto_wrapper failed" in PSoc Creator 4.2? @ https://community.cypress.com/message/159325
• Compile error with Creator 4.1 @ https://community.cypress.com/message/184795

Greg

Hello!

I have a project I described a few weeks ago here:

Can the CY4531 Evaluation Kit be used as a Client as opposed to a Host?

The idea is to use have CCG3 based clients, taking in up to 25W of power (@12V) each as well as USB data and Displayport:

In the thread linked above I learned that for the CCG3 EVK we would need to replace the standard CCG3 EVK mux with a Bi-Directional mux to support using the CCG3 EVK as a client rather than a host.

My question is on the firmware side of things for this change:

What are the firmware support options for a project of this kind?  Do any of the firmware projects included with the CCGx Host SDK support this functionality as-is?  Or will I have to be doing substantial modifications?

We are also looking to potentially use a TI TUSB1044 Bi-Directional USB-C mux rather than the Parade PS8742B in our design.  This is mostly due to part availability, we had a bit of a tough time getting our hands on the PS8742B, so we want to look into other options.  If I want to modify the firmware stack for the use of a new mux, where would I look to do so?  It looks like it should be mostly a modification of GPIO control and I2C commands, which hopefully shouldn't be too much of a problem, but I was hoping to get some additional opinions on considerations that need to be made when modifying for a different mux.

Thoughts/Opinions are welcomed!

Thanks in advance!

Hello,

According to the roadmap, CCG3PA2 solutions are already in production but I couldn't find any information, like a datasheet or hardware design guide on the website.

I'm especially interested in these chips since CCG3PA cries out for more flash and more IO pins, and CCG3PA2 seems to resolve these major drawbacks.

I need to disable the CYPD3177 to provide power from an external barrel power connector. I intend this power to come in after the pass fets that are controlled by VBUS_FET_EN. Can the VBUS_FET_EN be used for this purpose? Is there an alternate method?

Dear Sir/Madam,

Can you provide schematics and supporting documents for "CCG3PA USB-C(PPS) Power Bank Solution using Qorvo" from the link: https://www.cypress.com/documentation/reference-designs/ez-pd-ccg3pa-usb-cpps-power-bank-solution-using-qorvo-formerly

this question goes back to "locked memory" question. There is supposed to be an easy way to link it, but I cannot seem to find it. Would the following code segment work for this case? I tried this on my development platform CY4531 EZ-PD eval kit and now I cannot connect to reprogram the device from either the MiniProg3 or the Configuration utility tool. Third Eval kit down the tubes.  I would like to verify this before I try it again.  This time I will be using my last CY4541 eval kit.  This code will go in main before the infinite loop using the default notebook configuration.

uint8_t temp_buf[CCG_FLASH_ROW_SIZE] = {0};
uint8_t userIdWord;

userIdWord = *((uint8_t *)((CCG_APP_PRIORITY_ROW_NUM-1) << CCG_FLASH_ROW_SHIFT_NUM));
SW_Tx_UART_1_PutString("before userIdWord ");
SW_Tx_UART_1_PutHexByte(userIdWord);
SW_Tx_UART_1_PutCRLF();

/* Set APP Priority Field. */
temp_buf[0] = 0xAD;
if (CYRET_SUCCESS == CySysFlashWriteRow (CCG_APP_PRIORITY_ROW_NUM-1, temp_buf))
{
    SW_Tx_UART_1_PutString("good write");
    SW_Tx_UART_1_PutCRLF();
}
else
{
    SW_Tx_UART_1_PutString("fail write");
    SW_Tx_UART_1_PutCRLF();
}
SW_Tx_UART_1_PutString("after userIdWord ");
SW_Tx_UART_1_PutHexByte(userIdWord);
SW_Tx_UART_1_PutCRLF();

Due to CCG3PA VBUS_IN_DISCHARGE SPEC. is Max. 24.5V(30V tolerant)

So we had make CCG3PA with 24V sink application.

But CCG3PA will damage when VBUS over 20V, seems damage point around 22V above.

Does FW or HW need some implement for 24V application?

Thanks,

Mitchell

Hi!

Is there a way of enabling PPS on CYPD4226-based dock? Now with the standard finally coming out in products we get customer requests for this. We have a progarmmable DC/DC VBUS already in place. Noticed when we enable CCG_PPS_SRC_ENABLE that there is a stack call for dpm_pps_task(port) which doesn't seem to be available in the CYPD4226/Host SDK, only in the Power SDK.

Is there any hardware dependency towards the CCG3PA chipsets for this to work?  Noted in the product feature matrix that it was only CCG3PA that supported PPS, but isn't this something that could be implemented with additional SW and maybe HW using CCG4-based designs? Or you are not planning to release a lib for CCG4 that has the required PPS support?

We are typically looking at the 3.3V-5.9V and 3.3-11V PPS ranges.

Cheers

Olof

I have some questions about DMC,

1). How to know CCG4's US port is connected or disconnected with NB ?

2). How to send vendor data via HPI?  ( CCG4 --> DMC , DMC --> CCG4 )

1). We are develop product using CCGx SDK - CYPD3120.

it can FW upgrade by EZ-PD configuration utility but we need to customize it.

so please provide USB Bootloader windows F/W upgrade GUI example code to us .

2). We also try ADC  function on P2_4 pin and connect a VR (Variable Resistor) to P2_4 pin.

     below is our test code  :

     hsiom_set_config (GPIO_PORT_2_PIN_4, HSIOM_MODE_AMUXA);

     adc_level = pd_adc_sample(0, PD_ADC_ID_1, PD_ADC_INPUT_AMUX_A);

     hsiom_set_config (GPIO_PORT_2_PIN_4, HSIOM_MODE_GPIO);

     SW_Tx_UART_1_PutChar(adc_level);

     test result : P2_4 input voltage = 0 ~ 3.3V , level = 0 ~ 0xB5

     We get adc_level ragne is 0 ~ 0xB5, not what we expected 0 ~ 0xFF ( full range )

     How to solve it ?