CCG3PA - Rsense Bypass Capacitor - Schematic Review

[BiBr_4663101]

1. I've read in other discussions that a bypass capacitor should be placed across the Rsense resistor to reduce noise. Is a 100nf 50V MLCC cap good to use. Is there an optimum value to use?
2. I am using two CCG3PA-3175-24pin controllers. I would like to program both controllers using the same 6 pin header. Using an external mux one controller chip is progammed at a time. VDDD_C1, SWD_IO_PRI, SWD_CLK are active first while VDDD_C2 and SWD_IO_SEC are disconnected. Once the primary is completed VDDD_C2, SWD_IO_SEC, SWD_CLK are active and VDD_C1 and SWD_IO_PRI and disconnected. SWD_CLK is all the time running to both chips. If the chip that isn't being powered is receiving SWD_CLK will that load the clock line down or cause other issues I'm not aware. If this is ok to program this way, once programming is completed is this shared GPIO P0.1 connection between the controller chip usable.  We would like to use this shared connection as a way for the two controllers to signal a status.
3. Is it possible to email my schematic directly to someone for review?
4. Are pull-up resistors required on the I2C liines. Can they be enabled internal to the controller chip?

[RajathB_01 · Accepted solution]

Hello,

1. It can be used. There is no recommended value, you will have to select a capacitor as per your application constraints and layout considerations. Its recommended to simulate the performance as per your system noise levels and parasitics.

2. I do not see any problems with these connections. You can use the shared SWD_CLK pin for inter-chip signalling.

3. You can post your schematics here for review. If it is confidential, please use the direct message option to contact us and get your schematic reviewed.

4. External pull-ups are recommended for I2C lines.

Regards,

Rajath

[BiBr_4663101]

thanks for the response

My schematic has no low voltage regualtors. Can I connect 2k pull-ups to the controller chip VDDD?

[RajathB_01]

You can definitely do that. Please ensure the VDDD voltage level is in accordance with the supply of the I2C device at the other end. From your response I can deduce that VDDD of 3.3V is being sourced by the internal SHV VBUS LDO. May I know which is/are the other I2C device(s) here?

Regards,

Rajath

[BiBr_4663101]

Its another matching port controller. I were considering doing a total power balancing between the 2 controllers.

[RajathB_01]

Then you can safely pull the I2C lines to VDDD.

Regards,

Rajath