TRAVEO™ T2G Forum Discussions
Hi
I want to know the core power stabilization time when transitioning from DeepSleep to Active in CYT4BF.
I checked the power mode transition times according to the clock in the data sheet.
And in the application note, I confirmed that Core power switching is performed through HW operation when transitioning from DeepSleep to Active.
Q1) What is the core power stabilization time when transitioning from Deepsleep to Active in CYT4BF?
Q2) Does the power mode transition time in the datasheet include core power stablization time?
BR.
taegyunahn.
Show LessHello,
When exiting from Deep Sleep ,CLK_PLL400M0_STATUS,
UNLOCK_OCCURRED bit is getting reset, because of which peripheral is getting disturbed,
1> Does CLK_PLL400M0_STATUS->UNLOCK_OCCURRED getting changed can cause problem in peripheral?
2> How to set this bit ? What steps to be followed?
3> Does this bit get reseted after coming out of deep-sleep?
Show LessAfter the MCU is powered on, read the value of the RES-CAUSE register, sometimes 0x10000, sometimes - x40010000.The following diagram shows the waveform of the 3.3V power supply pin and XRES pin.
yellow-3.3V
green-XRES_L
1、why is RESET-PORVDDD sometimes 1 and sometimes 0?
2、Will external reset (XRES_L) clear the RESET_PORVDDD ? During actual testing, the MCU is operating normally, Make the XRES_L pin low , the RESET_PORVDDD will be cleared.
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Using tle9877, the flash is divided into two blocks for use (0x11000000~0x11002000 and 0x11002000~0x1100F00). After burning the two hex files corresponding to the partitions through jflash the program does not run.
Upon checking, both programs are runnable in keil emulation or via keil download.
smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/MOTIX-MCU/%E7%83%A7%E5%86%99hex%E5%90%8E%E7%A8%8B%E5%BA%8F%E6%97%A0%E6%B3%95%E8%BF%90%E8%A1%8C/td-p/699005
Show LessLIN_Master_example in TRAVEOII SDL "sdl_additional_code_examples_v7.5.0 w ex_control txt" is not working.
Specifically, it seems that the header signal does not sent from LIN CH2 TX on PORT P8_1, and the signal cannot be monitored by oscilloscope.
Is this code confirmed to work?
Also, has anyone actually been able to confirm this?
For inconsistencies between the sample codes, a header include was added to main_cm0plus.c of the sample code, and a macro prefixed with "LIN_" was prefixed with "CY_LIN_" and a function prefixed with "Lin_" was prefixed with "Cy_Lin_". Add define statement definitions.
Regards,
in Japanese/日本語
TRAVEOII SDL sdl_additional_code_examples_v7.5.0 w ex_control txtのLIN_Master_exampleが動作しません。
具体的にはPORT P8_1のLIN CH2 TXからのヘッダ送信がされないようで、オシロスコープから信号がモニタ出来ません。
こちらのコードは動作確認済みなのでしょうか?
また、実際に確認できている方はいらっしゃいますか?
なお、サンプルコード間の不整合のため、サンプルコードのmain_cm0plus.cにヘッダインクルードの追加とプレフィックス"LIN_"のマクロをプレフィックス"CY_LIN_"で、プレフィックス"Lin_"の関数をプレフィックス"Cy_Lin_"始まるようにdefine文定義を追加してます。
よろしくお願いいたします。
- Using sample code name as follow
- T2G_Sample_Driver_Library_7.3.0
- sdl_additional_code_examples_v7.5.0 w ex_control txt\sdl_additional_code_examples\07_LIN_Shield\LIN_Master_example
- Compiler
- IAR EWARM 8.42.2
- HW
- Traveo II Starter Kit CYTVII-B-E-1M-SK
- HW Config
- Jumper J17(D0-LIN) and J15(D1-LIN) are closed.
- Signal monitor location
- CON J10 pin1(port P8_1)
Is it possible to control the GPIO between the cores. In CYT2CL there are two cores CMO and CM4. I have a scenario where I need to toggle a GPIO Pin between the cores.
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I am porting from Traveo 1 (Traveo S6J32xx) microcontroller to Traveo 2 (CYT3DL) and I have a query related to "reset cause". In Traveo 1 Reset Factor section there is a "Software trigger hard reset"( SWHRST in RSTCNTR). I would like to know the equivalent reset factor/reset cause (RES_CAUSE) register in Traveo 2. Please let me know asap.
Show LessHi, I'm using the CYTVII-B-H-8M-176 development board, IAR 9.50.1
I have added my own program to the CM0 project, in which I will define some large arrays to be used for the program arithmetic. So far I have modified the three lines below the icf file.
But the compilation still encounters the problem of not enough SRAM, please see how to solve it, thanks.
smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/TRAVEO-T2G/IAR%E6%8A%A5%E9%94%99SRAM%E4%B8%8D%E5%A4%9F/td-p/700108
Show LessHi, I am using the CYTVII-B-H-8M-176 CPU BOARD development board which has a USB to uart interface.
I downloaded and installed T2G_Sample_Driver_Library_7.9.0, where tviibh8m\src\examples\scb\uart\ directory includes the main_cm7_0.c example of interrupt and polling, which I imported into tviibh8m\tools\ iar\flash\tviibh8m_flash_cm7_0_mc_template.eww project, after compiling and running are not able to see the serial port log output in USB to uart.
Querying the schematic document, I found that the two contacts on the board, TP185 and TP186, should correspond to the TX and RX of the serial port, but by connecting the USB-TTL directly to it, the PC could not see the log outputs, or send the content inputs, and the impact on the program flow.
May I ask what went wrong here?
smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/TRAVEO-T2G/TVIIBH8M-SCB-UART%E7%A4%BA%E4%BE%8B%E6%97%A0%E6%B3%95%E5%B7%A5%E4%BD%9C/td-p/697995
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