TRAVEO™ T2G Forum Discussions

Hi
I tested using CYT2B98, CYTVII-B-E-176-SO, and CYTVII-B-E-BB EVB.
A problem was discovered while testing ADC0 and ADC2 functions based on the SDL Adc Example code.
(SDL/tviibe2m/examples/adc/PhysicalChannel_to_DifferentLogicalChannel)

There are differences in ADC0 behavior depending on whether ADC2 is enabled or disable.
- ADC2 Disable: ADC0 conversion data normal.
- ADC2 Enable: ADC0 conversion data abnormal.

Details are below.

1. The SDL adc example code reads the voltage from the ADC through a potentiometer and then turns on the LED according to the adc conversion data.
   When ADC2 was enabled, the ADC0 conversion data was abnormal and the LED behavior was confirmed to be abnormal.
2. Currently, PERI_CLK of ADC0 and ADC2 is set to 13.3MHz (same as ADC Example)
   I confirmed that the problem was resolved by lowering ADC0 PERI_CLK to 6.66MH.
   (ADC0 conversion data is normal even if ADC2 is enabled)

Q1) Can the above problem occur, and are there any restrictions when using ADC0 and ADC2 together? It was confirmed that ADC2 operates normally regardless of whether ADC0 is activated, but only ADC0 appears to be affected by ADC2.

Q2) Are there any restrictions on PERI_CLK when using ADC0 and ADC2 together? (When using only ADC0, it operates normally even if PERI_CLK is set to 13.3MHz)

Additionally, I am attaching the code I tested.

Test method

1. Connect JP2.9 (P6.0: ADC[0]_0) of CYTVII-B-E-BB EVB to J89 (ADC_POT) Pin.1

2. USER_LED operates when controlling POT1 of CYTVII-B-E-BB EVB

Test code (It is almost the same as the SDL adc example)

1. Set ADC0, ADC2 peri clock

2. ADC0 Init

3. Perform ADC2 Init/DeInit operation every 5s in for loop.

(ADC0 peri clock change can be tested by modifying line 86.)

Thank you

Best & Regards

taegyunahn

While performing Deep sleep, before entering sleep Protocol error in arbitration layer detected bit in MTTCAN->IR register is reset, but after coming out of sleep this bit is set, what could be the possible issue in this case

你好，我想确认一下，在CM4内核上是否可以执行SRAM中的一段Flash驱动程序？

我遇到一个现象是，当SRAM中的Flash操作相关（Write）的程序运行时，如果ROM中的程序（CAN或者1ms cycle Reload Timer）的中断处理发生，那么会产生Hard Fault。回溯Hard Fault发生的位置，发现像是在ROM中的中断处理函数里发生的Fault的样子。

即使调低ROM中的程序的中断优先级到7，也不好用。但是如果把ReloadTimer停掉，即关闭掉Timer的中断那SRAM中的程序就会好用，并且没有Hard Fault。

期待您的回答，谢谢！

I am having a problem connecting to the CYT2B75CAD (CYTVII-B-E-1M-SK Starter Kit board) using the SWD and JLink segger.
Here is the message displayed on the j-flash:

Can you help please?

Hi

I'm using CYT4BF.

I had a problem while using SPI DMA, and I confirmed that it was working normally after disabling DCache.

And I was able to confirm that DCache was disabled in the SDL DMA Example.

(SDL_8.0.0/tviibh8m/examples/dma/pdma/dw_with_scb_uart/main_cm7_0.c)

Q1. What is the impact of using DCache when using DMA? 

Q2. Could you please tell me in more detail why DCache needs to be Disabled when using DMA?

Q3. Does disabling DCache (or ICache) affect ITCM and DTCM?
(I think it will affect Flash and SRAM, but I don't think it will affect ITCM or DTCM.)

Best & regards

Thank you.

taegyunahn.