Question about Traveo II MCU programming spec

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JackHsu_1153471
Level 3
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25 replies posted 50 sign-ins First like received

Hi,

I'm refer to the programming spec(002-22035 Rev. *B) of Traveo II to develop the programming algo.

Regarding to the CallSromApi subroutine, there is the description.

 

// Enable the notification interrupt of IPC_INTR_STRUCT[0](CM0+) for IPC_STRUCT[IpcId]
WriteIO IPC_INTR_STRUCT + IPC_INTR_STRUCT_INTR_IPC_MASK_OFFSET, 1 << (16 + 2));

 

May I know what definition is for IPC_INTR_STRUCT_INTR_IPC_MASK_OFFSET? 

I'm not it is typo or not. Thank you.

 

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1 Solution
Ashish
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25 likes received 50 solutions authored 100 replies posted

Hi ,

The definition of IPC_INTR_STRUCT_INTR_IPC_MASK_OFFSET appears to be missing in programming spec document, but the comment above the line mentions "Enable the notification interrupt of IPC_INTR_STRUCT[0](CM0+) for IPC_STRUCT[IpcId]" . So, you can refer the Register TRM of the target device , under IPC_INTR_STRUCT0_INTR_MASK (refer snapshot from TVII-BE-2M Register TRM below) . Since the parameter being passed is IPC_INTR_STRUCT + IPC_INTR_STRUCT_INTR_IPC_MASK_OFFSET,  so you can subtract the IPC_INTR_STRUCT value (0x40221000) to get the offset value (which should be 0x08 here). 

Ashish_0-1633360667424.png

 

Best Regards,

Ashish

 

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8 Replies
Ashish
Moderator
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Moderator
25 likes received 50 solutions authored 100 replies posted

Hi ,

The definition of IPC_INTR_STRUCT_INTR_IPC_MASK_OFFSET appears to be missing in programming spec document, but the comment above the line mentions "Enable the notification interrupt of IPC_INTR_STRUCT[0](CM0+) for IPC_STRUCT[IpcId]" . So, you can refer the Register TRM of the target device , under IPC_INTR_STRUCT0_INTR_MASK (refer snapshot from TVII-BE-2M Register TRM below) . Since the parameter being passed is IPC_INTR_STRUCT + IPC_INTR_STRUCT_INTR_IPC_MASK_OFFSET,  so you can subtract the IPC_INTR_STRUCT value (0x40221000) to get the offset value (which should be 0x08 here). 

Ashish_0-1633360667424.png

 

Best Regards,

Ashish

 

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JackHsu_1153471
Level 3
Level 3
25 replies posted 50 sign-ins First like received

Hi Ashish,

Thanks for your reply.

The Silicon ID is already read out correctly, but chip reports fail during erase all(Step3).

I measure the waveform and chip output 0xF1000107 in PollSromApiStatus function.

I think the CallSromApi should be work because Silicon ID is able to be read.

Do you have any suggestion? or what do you need more information?

Thank you.

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Hi ,

There could be multiple reasons that even though the reading the silicon id of chip is successful, the erase all is not success. However, the error code does not appear to be any one of the error-codes mentioned in Architecture TRM ( Table 33-92. System Call Status ), are you sure this is the error code? One reason  the API can return fail status is you do not have write access to flash according to SMPU settings(refer "Protection Unit" in Architecture TRM document).  

Ashish_0-1633447747270.png

 

What is the value you receive when you read silicon id (with ID=0, 1 and 2)? [refer Table  33-74 ,33-75 and 33-76 in Architecture TRM].

Regards,

Ashish

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JackHsu_1153471
Level 3
Level 3
25 replies posted 50 sign-ins First like received

Hi Ashish,

 

Thanks for your reply.

I refer to the  processing of Step2 in programming guide.

WeChat 圖片_20211006113352.png

There is the waveform about Silicon ID.

Dataout0 is FamilyID and RevisionID, and it outputs 0xA0230101.

WeChat 圖片_20211006113549.png

WeChat 圖片_20211006113528.png

Dataout0 is SiliconID and ProtectState and LifeCycleStage, and it outputs 0xA072E3DA.

WeChat 圖片_20211006113537.png

The Silicon ID is match as CYT2B75CADQ0AZEGS.

Regarding to Erase ALL waveform, it is process as below.

WeChat 圖片_20211006114514.png

it is CallSromApi process.

WeChat 圖片_20211006115126.png

There is the last waveform of  PollSromApiStatus (IpcAddr + IPC_STRUCT_DATA_OFFSET, data32), and output is 0xF1000107.

WeChat 圖片_20211006115325.png

Please let me know if you need more information.

Thank you.

Jack

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JackHsu_1153471
Level 3
Level 3
25 replies posted 50 sign-ins First like received

Hi Ashish,

 

Good day.

 

May I know any suggestions? 

In addition,  Which cypress programmer supports this series?

Thank you.

Jack

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Ashish
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25 likes received 50 solutions authored 100 replies posted

Hi Jack,

Can you please tell us how exactly are you programming/flashing , i.e. which programmer are you currently using? Also, would it be possible to test using Auto-Flash Utility tool (it's a command line Open OCD  based tool that can be used to program, verify and erase the TVII flash), and it works with Miniprog4 or Jlink programmer . Just wanted to see if the issue is with code or the flash itself. (You can also test on any other TVII device).

Link for Auto-Flash Utility: https://www.cypress.com/documentation/software-and-drivers/infineon-auto-flash-utility

Also, beside EraseAll, any other command failing? E.g. can you try Erase Sector and Program Flash? Let us know what is the response you receive.

Regarding your later question- As I told you can use Miniprog4 or JLink  with AutoFlash Utility to flash and erase. IDEs that can be used are IAR (with Ijet), GHS-Multi vs7, Lauterbach (TRACE32) for debugging purposes.

Thanks,

Ashish

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JackHsu_1153471
Level 3
Level 3
25 replies posted 50 sign-ins First like received

Hi Ashish,

 

Thanks for your reply.

We are third party programmer manufacturer.

I'm responsible to support TVII on our programmer.

I will use MiniProg4 with Auto-Flash Utility to test the device, and try to find the reason, and will update the status to you next week. 

BTW, Do you have the *.hex to test the TVII? if yes, could you help to provide the file to me for testing?

Thank you for great support and have a nice weekend.

Jack

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Hi Jack,

Sorry for delay in reply (I was on vacation last week). Please find attached zip for the hex file of TVII-BE-1M device (CYT2B7xx). This is a simple blinking LED project (if you use CPU board the user LED should blink, else kindly connect an LED to port-pin P8.2 .

Thanks,

Ashish

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