Jul 27, 2021
12:59 PM
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Jul 27, 2021
12:59 PM
Hi,
I am setting up cyt4bb PWM units, and have an annoying off-by-one with the timing somewhere in my code, so I thought to ask to confirm some details.
My TCPWM units are configured in PWM mode, up-counter, with a 480 clock PWM cycle (period reg = 479). The edges of the PWM pulses are generated by a mix of overflow and CC match events.
- It appears that in this case (PWM, up-counter), the "underflow" event does not trigger. Is that correct? I presume "overflow" is for counting up only and "underflow" is for counting down only?
- I'm unclear on whether the "overflow" event timing is equivalent to a CC0 match with CC0 = 479 (the period register value), or is equivalent to a CC0 match with CC0 = 0. Which is it (or something different)?
Solved! Go to Solution.
Labels
- Labels:
-
Automotive Traveo_II
1 Solution
Jul 27, 2021
03:45 PM
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Jul 27, 2021
03:45 PM
Ok, I re-read the TWM, and it seems Table 25-30 has the info I need:
- overflow is only generated when counting up, underflow only when counting down.
- overflow is generated when the counter wraps to zero (same timing as a CC match with value 0).
1 Reply
Jul 27, 2021
03:45 PM
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Jul 27, 2021
03:45 PM
Ok, I re-read the TWM, and it seems Table 25-30 has the info I need:
- overflow is only generated when counting up, underflow only when counting down.
- overflow is generated when the counter wraps to zero (same timing as a CC match with value 0).