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TRAVEO™ T2G

Venkatesh
New Contributor

Hi All,

Is there any way by which we can directly jump to M4 core by bypassing M0 core in Traveo II CYT2BL.

 

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Pranith
Moderator
Moderator

Hello @Venkatesh 

Bypassing CM0+ would not be possible.

Traveo II MCU’s boot sequence is based on the ROM boot code and flash boot code implemented for different lifecycle stages.
Figure attached shows how the CM0+ operation starts from reset. After reset, CM0+ starts executing from ROM boot. ROM boot validates SFlash. After validation of SFlash is complete, execution jumps to flash boot and configures the DAP as needed by the protection state. 

CM0+ image checks the digital signature authentication of the CM4/CM7image using the public keys that are programmed to SFlash.

You could have no user code on CM0+ and enable CM4 core  Cy_SysEnableApplCore(CY_CORTEX_M4_APPL_ADDR);

Regards

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Venkatesh
New Contributor

Hello Pranith,

Thanks for the information on boot sequence. 
Currently for running the CM4 core I have used the .out file of CM0+ core from the sample driver having and flashed along with my CM4 binary. 
I am facing a Hard fault exception from the code flash address. But when i checked the CPUSS registers for CM0+ status and CM4 status. I could see CM0+ is in sleep mode and CM4 is in a invalid state. Please find the images of the CPUSS registers and the maincm0_plus.c file used.

CPUSS_CM4_STATUS.png

CPUSS_CM0_STATUS.png

 Also I need to know that even if I do not need a secure boot up process as mentioned in the boot_TVII image. Do I need CM0+ core?

 

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