Traveo II MCU’s boot sequence is based on the ROM boot code and flash boot code implemented for different lifecycle stages. Figure attached shows how the CM0+ operation starts from reset. After reset, CM0+ starts executing from ROM boot. ROM boot validates SFlash. After validation of SFlash is complete, execution jumps to flash boot and configures the DAP as needed by the protection state.
CM0+ image checks the digital signature authentication of the CM4/CM7image using the public keys that are programmed to SFlash.
You could have no user code on CM0+ and enable CM4 core Cy_SysEnableApplCore(CY_CORTEX_M4_APPL_ADDR);
Thanks for the information on boot sequence. Currently for running the CM4 core I have used the .out file of CM0+ core from the sample driver having and flashed along with my CM4 binary. I am facing a Hard fault exception from the code flash address. But when i checked the CPUSS registers for CM0+ status and CM4 status. I could see CM0+ is in sleep mode and CM4 is in a invalid state. Please find the images of the CPUSS registers and the maincm0_plus.c file used.
Also I need to know that even if I do not need a secure boot up process as mentioned in the boot_TVII image. Do I need CM0+ core?
Are you observing this issue with the default sample code in the SDL? Could you check whether you have selected the correct device revision in your workspace setting? (see pic attached)? In order to conduct dual core debugging on IAR, you would have to compile and build the cm0+ and cm4 projects separately (ex: tviibe1m_flash_cm0plus_template and tviibe1m_flash_cm4_template) and then launch the dual core project (ex: tviibe1m_flash_cm0plus_cm4_template).