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TRAVEO™ T2G

M_F
New Contributor

How can the application distinguish CM7_0 and CM7_1 cores during runtime? Is there some core register that keeps the CPU index information (readable by application)? I have found only the CPUID register with identification of the CM0+ and CM7 but without index information.

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Swathi
Moderator
Moderator

Hi,

The expected values for the 'MS' field is given in the 'Table 22-1. Bus Masters for Access and Protection Control' of the device datasheet.

'PC' refers to the Protection Context of the current Bus master. It is used to restrict access to memory and peripheral resources. The value depends on how Memory Protection Unit is configured for that particular core. It ranges from 0 to 7. For more information on PC refer to the 'Protection Context' section of the device Architecture TRM.

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SwS_4081306
New Contributor

Hi,

The Arbiter (part of flash controller) performs priority-based arbitration based on the master identifier. Each bus master has a dedicated 4-bit master identifier. This master identifier is used for bus arbitration and IPC functionality. 

The 'MS' field of the CPUSS_IDENTITY register (in CYT4XX Registers TRM) specifies the bus master identifier of the current core. You can find the Bus master ID of the respective core in the device datasheet. 

 

M_F
New Contributor

Thank you for your answer. Unfortunately, I did not find an implementation-specific description of this register for Travel II derivatives. The values which can be expected in bit-fields "MS" and "PC".

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Swathi
Moderator
Moderator

Hi,

The expected values for the 'MS' field is given in the 'Table 22-1. Bus Masters for Access and Protection Control' of the device datasheet.

'PC' refers to the Protection Context of the current Bus master. It is used to restrict access to memory and peripheral resources. The value depends on how Memory Protection Unit is configured for that particular core. It ranges from 0 to 7. For more information on PC refer to the 'Protection Context' section of the device Architecture TRM.

View solution in original post