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TRAVEO™ T2G

Kwon
New Contributor II

I am curious about the following  Property of CAN Contoller.

  1. Synchronization Edge : Recessive to Dominant or Dominant to Recessive(The following is a description of other MCUs.)

Kwon_0-1629872831789.png

 

 

  1. Number of sample points

          In the following figure, it is the number of Sample Points.

Kwon_1-1629872831794.png

How can I check the above 2 properties?

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3 Replies
Pranith
Moderator
Moderator

Hello @Kwon ,

As pointed in the pic, each bit in the CAN frame is logically split into 4 time quantas or groups:
Sync_seg, prop_seg, Phase_Seg1, Phase_Seg2.
Synchronization segment is used to synchronize the nodes and is usually fixed to 1 time quanta.
The duration of other quantas or segments is programmable. Each bit duration is usually atleast 5 time quanta (min) and a maximum of 25 time quanta.
Regardless of combinational values of the segments, Phase_Seg2 has a minimum of 2 time quanta, this is to ensure that the bit duration is not shorter than information processing time (IPT).

In CAN, the nodes must be synchronised while receiving a transmitted bit, each of these received bits must occur during each node's Sync_Seg.
This type of synchronization is required to account for the phase difference between nodes operating at different oscillator frequencies or changes in propagation delay.
Two types of synchronization are defined in CAN: Hard synchronization and re-synchronization.

At the beginning of a message frame, every CAN node aligns the SYNC_SEG of its current bit time to the
recessive to dominant edge of the transmitted Start-Of-Frame bit. For a transmitting CAN node, the value of the bit is held from its Sync_seg to Phase_Seg2. All other active receiving nodes sync to the Sync_seg to receive data.
If a recessive to dominant bit value transition is detected outside of a receiving node's SYNC_SEG segment, then that node will re-synchronise to the edge.
The node will attempt to re-synchronize to the bit stream by increasing the duration of its PHASE_SEG1 segment of the current bit by the number of Time Quanta by which the edge was late.

Sampling point is the point at which the bus level is read and interpreted as the value at that respective time, choosing an optimum sampling point ensures robust CAN operation.
Misplaced sampling points can result in transmitter passive errors.

As an experiment you could alter the combinations of time quanta in the transmitting node to observe synchronization. 

Regards,

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Kwon
New Contributor II

In other words, is the Synchronization Edge = Received to Dominant, Number of sample points = 1?

Regards,

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Kwon
New Contributor II

2.  Number of sample points 

Kwon_0-1630472037240.png

 

in CYT2B93CAE, is the sample mode 1  or other value?

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