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TRAVEO™ II

balwant
New Contributor
Hello,
 
This is Balwant Godbole from KPIT technologies, Pune Inida. Currently we are working on cypress TRAVEO II series (VYT2B95bae) microcontroller. Using the CYT2B9 Datasheet, we started working on the interrupt information (mainly the address and mask information for INTR register and the MASK register to enable / disable the interrupt)
 
Out of the 383 interrupts listed in the datasheet, we could get the information (address & mask) for most of them except few interrupts. Below is the list of interrupts for which we need some support from cypress.
 
Int #      Source                                                    Power Mode               Description
47        cpuss_interrupts_cm4_fp_IRQn         Active                        Floating Point operation fault
48        cpuss_interrupts_cm0_cti_0_IRQn    Active                        Cortex-M0+ CTI #0
49        cpuss_interrupts_cm0_cti_1_IRQn    Active                        Cortex-M0+ CTI #1
50        cpuss_interrupts_cm4_cti_0_IRQn    Active                        Cortex-M4 CTI #0
51        cpuss_interrupts_cm4_cti_1_IRQn    Active                        Cortex-M4 CTI #1
 
The INTR address information and how to enable / disable these interrupts is not available in the datasheet and the user reference manual. Also, information is not available on internet.
 
For crypto interrupt, 
45          cpuss_interrupt_crypto_IRQn             Active                     CRYPTO Accelerator Interrupt
 
We could found the interrupt register address information in the cypress shared header files. However, the masking information and interrupt clear register description / information is not available in the "002-19567_0B_V - TRAVEO II AUTOMOTIVE BODY CONTROLLER ENTRY REGISTERS TECHNICAL REFERENCE MANUAL (TRM)"
 
We tried to get the information / support on internet forums, but could not revealed the correct information.
 
Can you please check and help us in resolving this? If required we can have meeting to discuss.
 
 
Thanks in Advance.
Regards,
-Balwant
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1 Solution
Ashish
Moderator
Moderator

Hi Balwant,

The CTI (cross trigger interface) and FP (floating point unit) are part of CPU core (CM0+ and CM4) specified by Arm, so kindly check in the ARM documentation on CM0+ and CM4 for core specific registers and interrupts to get more details. You can find some information on this in TVII- Register TRM in SYSTEM->CM0P and SYSTEM->CM4 . For Crypto- the registers related to this block are not exposed in register TRM , it's expected  to access through HSM performance library. However, if they are mentioned in SDL header file as you said, then you can use that for your reference. 

 

Thanks,

Ashish

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1 Reply
Ashish
Moderator
Moderator

Hi Balwant,

The CTI (cross trigger interface) and FP (floating point unit) are part of CPU core (CM0+ and CM4) specified by Arm, so kindly check in the ARM documentation on CM0+ and CM4 for core specific registers and interrupts to get more details. You can find some information on this in TVII- Register TRM in SYSTEM->CM0P and SYSTEM->CM4 . For Crypto- the registers related to this block are not exposed in register TRM , it's expected  to access through HSM performance library. However, if they are mentioned in SDL header file as you said, then you can use that for your reference. 

 

Thanks,

Ashish

View solution in original post

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