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TRAVEO™ II

chandan_R
New Contributor

Hello,

    We are using Traveo ii microcontroller (CYT2B97CAS QFP144).  We are trying to invert GPIO 15_3 with the help of smartio  and we configured the LUTs based on that. but we observed that configuration is not effective, we couldnot able to see inverted output at the pin.  Here I am attaching the trace32 configuration for that particular pin.

Please review the register configuration and suggest the right method to invert  the GPIO OUT pin using SMARTIO.

Thanks and Regards,

Chandan R

trace32.png

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3 Replies
Ashish
Moderator
Moderator

Hi Chandan,

 

Can you attach the code (or relevant code snippets where you configure SmartIO, and initialize it). What is the input signal that you are trying to invert on P15_3 using SmartIO? Is it coming from some other pin of Port-15 or some internal peripheral?

You can refer following AppNote which already describe on how to achieve this (refer section 4).

https://www.infineon.com/dgdl/Infineon-Smart_IO_Usage_Setup_in_Traveo_II_Family-ApplicationNotes-v01...

 

Best Regards,

Ashish

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chandan_R
New Contributor

Hello Ashish,

   Currently we are trying invert 15_3 digital output through smartio.

HSMIO(CHIP 15_3)  --> SMARTIO -->  PORTIO(15_3)

 

EB configuration and code snippet are attached, please guide us through.

 

 

chandan_R_0-1633067277459.png

 

chandan_R_1-1633067288050.png

 

 

FUNC(void,PORT_CODE) Port_Arch_Init
(
P2CONST(Port_ConfigType,AUTOMATIC,PORT_APPL_CONST) ConfigDataPtr,
P2CONST(Port_DriverEnvType,AUTOMATIC,PORT_CONST) EnvDataPtr
)
{
const Port_PinChannelConfigType* channelCfgPtr; /* ChannelConfigPointer */
uint8 portNr; /* port number */
uint8 cellNr; /* cell number */
uint8 count; /* counter for loop */
uint8 portCounter; /* counter for port number */
uint32 pinMask; /* bit position of current port pin */
uint32 cfgNotChangeMask; /* bit mask for CFG register */
uint32 outNotChangeMask; /* bit mask for OUT register */
uint32 out_value; /* OUT Register value */
uint32 out_write_value; /* OUT Register write value */

/* Enter critical section to provide atomic access to the port registers */
Port_EnterCriticalSection();

/* loop for all AMUX splitter cells */
for ( count = 0U; count < ConfigDataPtr->numberOfAmuxSplitCtl; count++ )
{
/* Gets physical cell number */
/* Deviation from MISRA-C:2004 rule 17.4
Justification: Implementation often uses pointer access by
array-subscripting. */
/* PRQA S 491 1 */
cellNr = ConfigDataPtr->configAmuxSplitCtlPtr[count].amuxSplitCtlNumber;
/* Sets value to AMUX_SPLIT_CTL Register */
/* Deviation from MISRA-C:2004 rule 17.4
Justification: Implementation often uses pointer access by
array-subscripting. */
/* PRQA S 491 1 */
Port_WriteAMUX_SPLIT_CTL(EnvDataPtr, cellNr, ConfigDataPtr->configAmuxSplitCtlPtr[count].AMUX_SPLIT_CTL_Data);
}

/* Exit critical section */
Port_ExitCriticalSection();

/* loop for all available ports */
for ( portCounter = 0U; portCounter < ConfigDataPtr->numberOfPorts; portCounter++ )
{
/* Gets configChannelPtr. */
/* Deviation from MISRA-C:2004 rule 17.4
Justification: Implementation often uses pointer access by
array-subscripting. */
/* PRQA S 491 1 */
channelCfgPtr = (const Port_PinChannelConfigType*)&ConfigDataPtr->configChannelPtr[portCounter];
/* Gets physical port number */
portNr = (channelCfgPtr)->portNumber;

/* Enter critical section to provide atomic access to the port registers */
Port_EnterCriticalSection();

/* Calculates mask value for CFG Register and OUT Register */
Port_Arch_CalcRegMaskValue(channelCfgPtr, EnvDataPtr, &cfgNotChangeMask, &outNotChangeMask);
/* Gets value of OUT Register */
out_value = Port_ReadOUT(EnvDataPtr, portNr);
/* Calculates write value of OUT Register */
out_write_value = (out_value & outNotChangeMask) |
((channelCfgPtr)->OUT_Data & (~outNotChangeMask));

/* First, Sets value other than pins that do not need to be changed
in the CFG register */
Port_WriteCFG(EnvDataPtr, portNr, ((channelCfgPtr)->CFG_Data & cfgNotChangeMask));
/* CTL register shall be written: Disable SMARTIO with 'ENABLED' field */
Port_WriteCTL(EnvDataPtr, portNr, 0U);

/* Sets value to OUT Register */
Port_WriteOUT(EnvDataPtr, portNr, out_write_value);
/* Sets value to PORT_SEL0 Register */
Port_WritePORT_SEL0(EnvDataPtr, portNr, (channelCfgPtr)->PORT_SEL0_Data);
/* Sets value to PORT_SEL1 Register */
Port_WritePORT_SEL1(EnvDataPtr, portNr, (channelCfgPtr)->PORT_SEL1_Data);

/* Sets value to SYNC_CTL Register */
Port_WriteSYNC_CTL(EnvDataPtr, portNr, (channelCfgPtr)->SYNC_CTL_Data);

/* loop for available pin for a port */
for ( count = 0U; count < (PORT_MAX_PIN / PORT_MAX_PORT); count++ )
{
pinMask = ((uint32)1U << count); /* Gets pin position for loop count */

/* Checks "current loop count is available pin" */
if ( ((channelCfgPtr)->availablePins & pinMask) != 0U )
{
/* Sets value to LUT_SEL Register */
Port_WriteLUT_SEL(EnvDataPtr, (Port_PortType)portNr, (Port_PinType)count,
(channelCfgPtr)->LUT_SEL_Data[count]);
/* Sets value to LUT_CTL Register */
Port_WriteLUT_CTL(EnvDataPtr, (Port_PortType)portNr, (Port_PinType)count,
(channelCfgPtr)->LUT_CTL_Data[count]);
}
}

/* Sets value to DU_SEL Register */
Port_WriteDU_SEL(EnvDataPtr, portNr, (channelCfgPtr)->DU_SEL_Data);
/* Sets value to DU_CTL Register */
Port_WriteDU_CTL(EnvDataPtr, portNr, (channelCfgPtr)->DU_CTL_Data);
/* Sets value to DATA Register */
Port_WriteDATA(EnvDataPtr, portNr, (channelCfgPtr)->DATA_Data);

/* Sets value to CFG_IN Register */
Port_WriteCFG_IN(EnvDataPtr, portNr, (channelCfgPtr)->CFG_IN_Data);
/* Sets value to CFG_OUT Register */
Port_WriteCFG_OUT(EnvDataPtr, portNr, (channelCfgPtr)->CFG_OUT_Data);
/* Sets value to CFG_SIO Register */
Port_WriteCFG_SIO(EnvDataPtr, portNr, (channelCfgPtr)->CFG_SIO_Data);
/* Sets value to DFT_SIO Register */
Port_WriteDFT_SIO(EnvDataPtr, portNr, (channelCfgPtr)->DFT_SIO_Data);
/* Sets value to CFG_IN_GPIO5V Register */
Port_WriteCFG_IN_GPIO5V(EnvDataPtr, portNr, (channelCfgPtr)->CFG_IN_GPIO5V_Data);
#if (PORT_CLUSTER_DEVICE == STD_ON)
/* Sets value to CFG_OUT2 Register */
Port_WriteCFG_OUT2(EnvDataPtr, portNr, (channelCfgPtr)->CFG_OUT2_Data);
#endif

/* Finaly, Sets value to CTL Register for SMARTIO */
Port_WriteCTL(EnvDataPtr, portNr, (channelCfgPtr)->CTL_Data);
/* And Sets value to CFG Register for GPIO */
Port_WriteCFG(EnvDataPtr, portNr, (channelCfgPtr)->CFG_Data);

/*--------------------------------------------------------------*/
/* CTL register shall be written: Disable SMARTIO with 'ENABLED' field */
// Port_WriteCTL(EnvDataPtr, 6, 0U);
// Port_WriteSYNC_CTL(EnvDataPtr, 6, SMARTIO_IOSYNC_CH_MASK);

/* Exit critical section */
Port_ExitCriticalSection();
}


}

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Ashish
Moderator
Moderator

Hi Chandan,

The MCAL related queries are subject to NDA  , so we can not proceed here on community, but we will get back to you through other channel to proceed further.

Thanks,

Ashish

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