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TRAVEO™ II

rloader
New Contributor II

Hi, any advice on this problem welcome.

I have some software running on a cyt4bb with Cypress SDL version 6.4.0, but am running into probems with SDL version 7.2.0. (I am attempting to use the cyt4bb/rev_b support in SDL 7.2.0, SDL 6.4.0 only supported rev_a)

The symptom is that SystemInit() on the CM0+ gets stuck in the power management code, the stack trace is:

Cy_SysReghc_IsSequencerBusy
SwitchToExternal
Cy_Power_SwitchToPmic
SystemInit
main

I have verified with a multimeter that both the 3.3V (actually 3.22V) and 1.1V to the CPU appear to be correct.

The clocking to the board is a bit different from the "cypress default": there is a 12MHz ext. oscillator, not a crystal. Because of that, I am attempting to boot the CM0+ using the IMO instead of ECO. To that end I have changed two lines in system_cyt4bb.h:

#define CY_SYSTEM_USE_CLOCK CY_SYSTEM_USE_IMO
#define CY_CLK_EXT_FREQ_HZ ( 12000000UL)

(The code as delivered from Cypress has ...USE_ECO and 0 respectively for the two items above.

Cheers,
Ralph.

 

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1 Solution
rloader
New Contributor II

We solved the issue - we needed to change the #define CY_SYS_VCCD_SOURCE to match our power supply circuitry - I had simply missed that in the migration between SDL versions.

View solution in original post

2 Replies
Ashish
Moderator
Moderator

Hi Ralph,

Are you trying default SDL example? What are the modifications that were done in the code (like you mentioned changing clock from ECO to IMO in system_cyt4bb.h file). Can you attach the main.c and system_cyt4bb.h file?

Also, please check all the voltages (VCCD, VDDD, VDDA AND VDDIO) on the board , and let us know it's values.

 

Thanks,

Ashish

 

0 Likes
rloader
New Contributor II

We solved the issue - we needed to change the #define CY_SYS_VCCD_SOURCE to match our power supply circuitry - I had simply missed that in the migration between SDL versions.

View solution in original post