I am setting up cyt4bb PWM units, and have an annoying off-by-one with the timing somewhere in my code, so I thought to ask to confirm some details.
My TCPWM units are configured in PWM mode, up-counter, with a 480 clock PWM cycle (period reg = 479). The edges of the PWM pulses are generated by a mix of overflow and CC match events.
It appears that in this case (PWM, up-counter), the "underflow" event does not trigger. Is that correct? I presume "overflow" is for counting up only and "underflow" is for counting down only?
I'm unclear on whether the "overflow" event timing is equivalent to a CC0 match with CC0 = 479 (the period register value), or is equivalent to a CC0 match with CC0 = 0. Which is it (or something different)?