Can we use 3.073MHz as I2S clock for "48kHz, 16 bits, 2 channels" ?
The data rate is "48kHz, 16 bits, 2 channels -> 1.536 Mbps".
So, the clock rate is higher than the data rate.
Can CYBT343026 accept the settings ?
If yes, I think some padding data will be inserted in it.
Is the followings correct ?
<Lch(16bit: MSB->LSB), padding(16bit)>, <Rch(16bit, MSB->LSB), padding(16bit)>, <Lch, padding>, <Rch, padding>, ...
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I do not understand your query correctly. What do you mean by clock rate and data rate?
At I2S slave side, you don't have to set anything. WICED slave device will take care of the clock depending on the master clock. Just make sure that we support only 16 bit configuration.
When A2DP data is "48 kHz, 16 bits, 2 channels", can we use 3.072MHz as I2S clock ?
What do you mean by A2DP data is "48 kHz, 16 bits, 2 channels"? You mean 1.536 MHz clock?
When A2DP Source data is 48kHz, 16 bits, 2 channels, then data rate is 1.536 bps.
In this case,
Do we have to use just 1.536MHz as I2S clock ?
Or, can we use any rate higher then 1.536MHz ?
As given in PCM/I2S Clock setting in CYW20706 , WICED device I2S master only supports 1.536 MHz clock.
Whether as, if you are using some other I2S master (other than WICED device), then WICED device I2S slave rate can be upto 3.072 MHz, which is set by I2S master itself. You don't have to set the slave frequency separately; just configure the device as I2S slave.
As you wrote, I2S slave doesn't set clock rate.
So, if I2S master use 3.072MHz as I2S CLK, how does CYBT-343026-01 handle A2DP data which is encoded by 48 kHz 16 bits, 2 channels ?
Please find I2S_CLK3.072MHz_48kHz_16bit_2ch.png at response_#6 above.
I'm sorry for rushing you, but It would be appreciate to reply soon.
In other words, does CYBT343026 support the signals with padding likes the attachment in I2S slave mode ?