- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello, I'm working on a design with CY7C4122KV13. As per the warnings in the data sheet, the use of TRST# is not optional for this device. I intent to use JTAG. In the reset sequence (page 11) step 1 says we have to start out with RST# and TRST# low. In none of the following steps does it say what you need to do with TRST#, and when. I'm trying to keep this simple, and not have to have do something like have logic gates with reset as an input to drive TRST. What exactly do I need to do with it?
Solved! Go to Solution.
- Labels:
-
Memory SRAM
- Tags:
- jtag
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi @u2482 ,
In the datasheet, on page no. 20, it is mentioned that the TRST# input pin is used to reset the TAP controller. So, TRST# should be made low during tPWR, which is mentioned in the reset sequence section (page no. 11) and if you want to reset the TAP controller, it should be made low for at least tTSS (min 200 us).
Thanks,
Ritwick
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi @u2482 ,
In the datasheet, on page no. 20, it is mentioned that the TRST# input pin is used to reset the TAP controller. So, TRST# should be made low during tPWR, which is mentioned in the reset sequence section (page no. 11) and if you want to reset the TAP controller, it should be made low for at least tTSS (min 200 us).
Thanks,
Ritwick