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SRAM

Anonymous
Not applicable

 Is there any reference design for CY7C1481BV25 you guys mind to share? 

   

I want to use two CY7C1481BV25 so I can get 72bit data length and I wanted to be sure that I'm not missing anything cause I've never worked with SRAMs !

   

Thank you.

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1 Solution
Anonymous
Not applicable

 Hi,

   

I reviewed the schematic and find that series termination is being used. 

   

1. ZZ Pin has an internal pull down. For normal operation you can tie it to LOW or leave it floating.

   

2. MODE Pin has an internal pull up. So when left floating or tied to Vdd, it uses interleaved burst sequence.

   

You can add an external pull-up on all active low control signals. When the FPGA drives a LOW, the corresponding signal gets activated.

   

Even for the clock, you can add a Pull-Up resitior externally or directly drive the CLK from the FPGA.

   

Thanks and Regards

   

PSoC Wonders 

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Anonymous
Not applicable

 Hi Mostafanfs,

   

Firstly, please not that CY7C1481BV25 is Not Recommended For New Designs. The closest alternative is CY7C1481BV33.

   

We are sorry to say that currently we don't have any reference schematic design for Standard Sync SRAM. However, since the part operates at comparatively low frequency, we can connect it pin to pin (from FPGA to Memory). But we always recommend our customers to perform SI Simulations for the same and check if the signals look good with or without terminations.

   

 

   

     

 

   

If you would like to add termination resistors, then  it is typically recommended to use series termination or pull-up (pull-down) termination on the clocks and the data signals, and optionally on the address and the control signals depending on how the signal integrity looks. Please check this link for more details:     

 

   

http://www.cypress.com/?id=4&rID=30075     

 

   

One thing which you might have to take care would be the decoupling capacitors to be used in the design. I think the following article would help you with the Design of Decoupling Capacitors

   

We can also review your schematic once you are done with the same.

   

 

   

Regards

   

PSoC Wonders

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Anonymous
Not applicable

 Thank you for your answer

   

Actually attached file is my schematic. I will notice your comments and I will do some Signal Integrity using provided IBIS model. But besides the termination part I'm not sure about Control and Enable Pins. Do I need Pull-up or Pull-down resistors on those signals ? (GW,CLK,CE1,CE2,CE3,OE,ADV,ADS,ADS,BWE,ZZ,MODE). I couldn't find out this from the datasheet.

   

I really appreciate it if you review the schematic file.

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Anonymous
Not applicable

 Hi,

   

I reviewed the schematic and find that series termination is being used. 

   

1. ZZ Pin has an internal pull down. For normal operation you can tie it to LOW or leave it floating.

   

2. MODE Pin has an internal pull up. So when left floating or tied to Vdd, it uses interleaved burst sequence.

   

You can add an external pull-up on all active low control signals. When the FPGA drives a LOW, the corresponding signal gets activated.

   

Even for the clock, you can add a Pull-Up resitior externally or directly drive the CLK from the FPGA.

   

Thanks and Regards

   

PSoC Wonders 

View solution in original post

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