PSoC™ Creator & Designer Forum Discussions
When using the DelSig at high resolution there are many considerations
that come into play. A good example is the design consideration doing a load
cell over large dynamic range.
If we use DelSig at 20 bits, 1.024 Vref, range +/- 1.024, then 1 LSB = ~ 2 uV.
If we look at lead free solder, the seebeck coefiicient is ~ 2 uV / 0K (consult solder
datasheet). So for a 50 C rise in design, each transition junction on the board yields
50 LSBs of error. If in diff mode, and junction count equal on each input, then this
gets eliminated. You can have an imbalance of junctions in chained ground layouts,
signal path nodes not present in ground path, etc., thats when your problems multiply.
Diff mode and layout practices ways of handling this.
Also PSRR in any signal path components, like an OpAmp, can add to this. For
example if PSRR is 60 db, Vdd changes by 100 mV, then that yields OpAmp output
change of 100 uV, another 150 LSBs of error.
Noise, CMRR, thermoelectric effects, INL, DNL, additionally all have to be considered.
Just some of many considerations in attached ap notes, look at AN280 first.
Regards, Dana.
Show LessMy program fails to compile after I upgraded from 5.3 to 5.4.
The error is:
!E C:\...\main.h(15): cannot include source file "stdint.h"; file not found
The line 15 is:
#include<stdint.h>
Of course, if I comment out that line, I get errors all over the place regarding the use of int16_t etc.
For now, I'll just copy the stdint.h file to the project directory, but can someone give a cleaner solution?
Thanks,
Paul
Show LessWould be nice, when configuring the DelSig, if to the reight of the resolution setting,
you show, for the set reference and input range, the equivalent value of an LSB in uV.
Also a graphic picture of CM range for the inputs for the specific settings chosen.
Regards, dana.
Show LessJust encountered a strange problem. I took a project from 2.2 SP1 and imported it into 3.0. I can compile and execute the code just fine in Debug mode. However, when the code is compiled in release mode, it fails to execute. In other words, the processor appears to hang. This is on a CY8C4125.
I did not have this issue in 2.2 SP1.
Thoughts?
Show LessCypress and element14 are pleased to annouce the PSoC 4 Smarter Life Design Challenge!
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Show LessWhen Cypress provides a fix like this I think, for many reasons, should be
offered as a Windows Script. Minimizes errors, insures commands are typed
properly, exposes OS differences.......saves all time.
http://www.cypress.com/?app=forum&id=1573&rID=86197
Regards, Dana.
Show LessHi,
I have 8 pins input and 8 as output.
I would like to change connections between them during runtime.
Please see attached 2 pictures for reference.
Please give me a hint how should I make this.
Kind REgards,
Daniel
Show LessHi,
I just wanted to set a RTC to European standards for DST which is
DSTStart : Last Sunday in March
DSTEnd : Last Sunday in October
Since I can set the week with RTC_WriteDSTStartWeek(Week), there is not a chance to set Week to the LAST week.
Besides calculating the number of Sundays for a given month myself, I would rather prefer to specify "5" for the week and let the RTC adjust it to the correct value which would be 4 or 5 (There are never more than 5 Sundays in a month and never less than 4)
Is there a chance that the RTC-Module will be updated to reflect the European Standards as of 2000/84/EG ORDERING of DAYLIGHT-SAVING-TIME?
THX
Bob
Show LessWhen configuring the DelSig there is a mislabeling of input buffer mode
as meeting R-R performance. As shown below industry standard includes
the rails in CMI range, which the input buffer does not.
However, that being said, you do not label bypass buffer mode as R-R, which
it should be. Further you should call it "R-R Plus", as it exceeds R-R performance,
and as such is very useful for some design problems.
Lastly you could clear up a lot of confusion, as witnessed by the number of forum
postings, if you offered those images of input range tied to input range selection
box, ie. show user actual range he is going to get graphically.
Show Less