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PSoC™ Creator & Designer

Anonymous
Not applicable

Hi,

   

I'm a newcomer to PSOC, and have been playing around with a CY8CKIT-049 board.  I have a few projects in mind where these devices will be ideal - but I've hit a snag with a verilog component.

   

I've attached the simplest project possible which shows the problem - but in short, I have three inputs to my custom component.  A signal is mutiplexed to one of two input signals according to the state of a third, and then the output (a bidir pin) is set either to 1'bz or 1'b0 according to the state of the multiplexed signal.

   

It's easier to express in verilog than English - and looks like this:

   

wire output_signal_out;
assign output_signal_out = sel ? input_signal : input2;
assign output_signal = (output_signal_out ? 1'bZ : 1'b0);

   

 

   

When I compile it, however, I get the following message in the "output" tab:

   

ERROR: BiDirTest.vh2(40,4) : Unexpected token '!'. Expected '<=', or ':'
ERROR: BiDirTest.vh2(43,2) : Unexpected token 'Net_2'. Expected '<=', or ':'

   

 

   

Looking at the VH2 file, the offending lines are:

   

IF !(\component01_1:output_signal_out\) THEN
    Net_2 <=  ('0') ;
ELSE
    Net_2 <= 'Z';
END IF;

   

 

   

Any ideas?  Have I been unlucky enough to hit a compiler bug on my first project?  Or am I doing something wrong?

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10 Replies
Bob_Marlowe
Expert II

The negation (!) has to be WITHIN the parentheses, not before.

   

 

   

Bob

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Anonymous
Not applicable

Thanks Bob.

   

The .VH2 file is automatically generated from my verilog code, though - so if I fix it in there, it'll just be overwritten next time I build, yes?

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Bob_Marlowe
Expert II

I overlooked that you were talking about a .vh2 - file. So I cannot say where your error comes from. Check your verilog?

   

 

   

Bob

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Bob_Marlowe
Expert II

Can you please post the complete project. Use Creator -> File -> Create Workspace Bundle and then attach the resulting archive (do NOT use chrome, will not work).

   

 

   

Bob

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Anonymous
Not applicable

OK no problem - zipfile attached.

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Anonymous
Not applicable

Well I definitely attached the zipfile (using firefox) but I can't see it attached to my post?

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Anonymous
Not applicable

Let's do it the old-fashioned way, then: the project file can be found here: http://retroramblings.net/temp/BiDirTest-000.cywrk.Archive01.zip

   

(The simplest testcase I could construct that exhibits the problem.)

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Bob_Marlowe
Expert II

Now I can see what you want. The fitter gives an error because you try something in verilog that cannot be performed by the hardware: Driving an INTERNAL signal to Hi-Z.

   

When you want to use a PIN's output as Hi-Z, you will have to use the oe (output enable) signal to control this.

   

Btw: Use ms internet explorer to attach files, firefox SOMETIMES has problems here. Not your fault, but the forum-software is from the last century

   

 

   

Bob

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Anonymous
Not applicable

Ah - thank you  -  I wondered if I was trying to treat the PSOC too much like an FPGA!  I have to learn to think a little differently, obviously. 🙂

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Anonymous
Not applicable

For the benefit of anyone else with the same question, I was over-thinking this problem, and what I actually needed was simply a bidirectional pin with the output drive mode set to "Open drain, drives low".

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