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PSoC™ Creator & Designer

RaAl_264636
Contributor II

Hi,

   

 

   

I 'm new to PSoC and want to dig deeper into it So I bought a PSoC 4 pioneer kit as a starting point.

   

Now, I want to go for my 'real' first own design. This design uses a shift register component.

   

 

   

I've some questions:

   

1) It seems a counter is necessary to detect if the desired number of bits have been shifted, right?

   

2) I want to generate an interrupt if a new byte has been loaded from the FIFO into the shift register. I don't use the load input signal, but it seems that the load interrupt output can still be used for that purpose, right?

   

3) Is it possible to access the shift register status register (or the underlying UDB) by hardware? I want to detect if the FIFO is empty.

   

 

   

Regards,

   

 

   

Ralf

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16 Replies
Bob_Marlowe
Expert II

Hi Ralf, welcome in the fascinating world of PSoCs!

   

First the bad news: there is no signal of the shift register to indicate it is containing all zeroes.

   

The better news are: you might define (program) an UDB to be a shift-register with a all-zero signal.

   

The next bad news is: That turns out to be complicated since you will have to learn and use a "Hardware Description Language" (HDL) named "Verilog". On top of this page is a "Keyword Search" field, enter "UDB" or "Verilog" or both and get something to read or watch.

   

 

   

Bob

   

PS: Are you German? Where are you located?

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RaAl_264636
Contributor II

Hi Bob,

   

 

   

thank you for answering 🙂

   

 

   

First the bad news: there is no signal of the shift register to indicate it is containing all zeroes.

   

Maybe a missunderstanding: I don't want to detect if the shift register contains all zeros, but if the FIFOs of the shift register component are empty.

   

 

   

The better news are: you might define (program) an UDB to be a shift-register with a all-zero signal.

   

I thought it's maybe possible to modify the existing component

   

 

   

The next bad news is: That turns out to be complicated since you will have to learn and use a "Hardware Description Language" (HDL) named "Verilog". On top of this page is a "Keyword Search" field, enter "UDB" or "Verilog" or both and get something to read or watch.

   

Shouldn't be a problem to learn it. But the key is to write it efficient 😉

   

 

   

PS: Are you German? Where are you located?

   

Ja, bin ich 😃 Im Schwarzwald.

   

 

   

Regards,

   


Ralf

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Bob_Marlowe
Expert II

Shouldn't be a problem to learn it. But the key is to write it efficient. No need, there's an optimizer integrated, but getting it error-free and fitting into an UDB is the goal.

   

For the empty-flag: Look into the datasheet (Page 10) regarding GetFIFOStatus().

   

 

   

Bob (Bremen)

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RaAl_264636
Contributor II

Hi Bob,

   

 

   

sorry for the scribbled posting, I didn't notice that the formatting (italic, etc for quoting) has been gone 😞

   

Seems I'm fighting with the forum software, I don't know what I'm missing 😐

   

 

   

I try it again with the formatting options:

   

For the empty-flag: Look into the datasheet (Page 10) regarding GetFIFOStatus().

   

Yes, I saw it, but it needs the software to poll for it. My idea was if it's possible to extend the existing component with a FIFO empty output.

   

You're right, it should also be possible to write a complete new tiny shift register component - a good exercise 😉

   

 

   

Regards,

   

 

   

Ralf (VS-Schwenningen)

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Bob_Marlowe
Expert II

You are not the only one here (and I'm afraid there will be some more coming) who is fighting with the forum software. Best is: Do not try anything, even when it seems to be simple

   

Use IE when attaching files, rumors tell that firefox will do as well, chrome definitively will NOT work.

   

Project questions can be solved quickly when you attach a "Workspace Bundle" which not only will contain your code, but your component and compiler settings, too.

   

There is a blog from Brad Budlong concerning verilog components, that was very helpful for me. When you know how to create new components you will know how to modify existing ones (without destroying the original

   

 

   

Bob

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RaAl_264636
Contributor II

Hi Bob,

   

 

   

this sounds good. I started with the application notes regarding component creation (AN81623, AN82156 and AN82250), I think I have a base how to start.

   

Currently I'm on pen and paper, making notes, etc. In short, the whole design encodes the single bits of a software buffer into pulses with different pulse widths.

   

The purpose of the shift register is to fed a PWM component with fixed frequency and two fixed pulse widths (the PSoC 4 fixed timer/PWM module will be suitable, I think). The pulse width defines if it's a low or a high bit. The design needs to output the pulses continously as long as bytes are present in an software buffer with no delay between the bit pulses. If the buffer has been completely shifted out, the data signal must be go into an idle state.

   

So, my shift register needs to use the FIFOs, the FIFO status signals and if possible a bit counter to make the idle state easier.

   

Now, I'll try to make an assumption which of those functions will go into a datapath and which will be solved by the PLD 😉

   

 

   

Regards,

   


Ralf

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HeLi_263931
Honored Contributor II

This sound like you are re-implementing SPI... I would that try first: use a UDB-based SPI component, and feed its data signal to the PWM switch input. The SPI component already does everything you need.

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RaAl_264636
Contributor II

Hi hli,

   

 

   

yes, it's some kind of SPI. I'll try your suggestion if I can't get an own component to work. Otherwise I couldn't learn PSoC in detail

   

I'll look into the SPI component how it's realized, good idea, thanks.

   

 

   

Regards,

   

 

   

Ralf

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Bob_Marlowe
Expert II

Don't you think that it is a rather heavy start with PSoCs to begin with a DataPath object? Wouldn't it be better to get acquainted to Creator and the capabilities of PSoC4 (which are a bit reduced compared to the PSoC5).

   

 

   

Bob

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RaAl_264636
Contributor II

Hi Bob,

   

 

   

yes, it's heavy 😉 It's the hard way of learning by doing. However, I can still switch and build it up with the supplied components if my approach won't work.

   

Currently it seems that the example code of AN82156 (the UART Tx component) will be a good base. If I can modify it to fit my needs I should maybe also be capable to implement the PWM portion in that component, without using the seperate PWM component.

   

But step by step... 😉

   

 

   

Regards,

   

 

   

Ralf

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Bob_Marlowe
Expert II

Well, then: Get it working

   

 

   

Bob

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RaAl_264636
Contributor II
        Hi Bob, I'll do 😉 One question: how can I determine if my solution is 'good'? Is it simply 'if it fits completely into one UDB it's good'? Regards, Ralf   
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Bob_Marlowe
Expert II

Primarily: your component must work correctly and fit into the two USBs a PSoC4 has got. Remember for future projects: a PSoC5 has got 24 UDBs and there is a rather comfortable development kit for this, but it is more expensive than a Pioneer board.

   

You have to prove that your implementation works, so you will need a logic analyzer. If you haven't got one, I can point you to a cheap source. VeriLog does not allow for debugging and simulation, so proving the correctness can turn out to be difficult.

   

The criteria for something to be "good" differs from the point of view and the context you are in. In the world of PSoCs "good" could mean "cheap". So how to be "cheap" when producing a component? "Quick & dirty" has turned out to be not "cheap", instead it could get expensive. I am really convinced that "cheap" is related to "easy to understand" which needs something I call "readability". The quintessence of this is: Write down everyting with understanable names in an easy-to-understand structure with only the necessary documentations. This will help you in, say 3 months, when picking up the sources again to understand which strike of genius had hit you when you wrote down that lines.

   

 

   

Bob

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RaAl_264636
Contributor II

Hi Bob,

   

 

   

what do you mean by 'two USBs a PSoC4 has got'? Do you mean UDBs? If yes, if I'm correct a PSoC4 has 4 UDBs.

   

 

   

Good hint with the logic analyzer. If it doesn't cost too much I'll buy one maybe. Otherwise I've to try to verify it with an oscilloscope.

   

 

   

I agree with your definition of 'good' and 'cheap'. I assume my first try will waste some ressources and will also be written 'scribbled' until I get a feeling for it 🙂

   

 

   

Regards,

   

 

   

Ralf

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Bob_Marlowe
Expert II

Yes, UDBs of course! I've got a cut in my index-finger and the plaster is a bit broad  for one keystroke.

   

Logic analyzer: have a look here: http://ikalogicstore.com/ there are 3 different modules.

   

 

   

Bob

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RaAl_264636
Contributor II

Hi Bob,

   

 

   

those LAs look nice. I'll compare them with the LAs I already know from other vendors 🙂

   

Currently I'm modifying the AN82156 UART_TX example component for my purpose 😄

   

 

   

Regards,

   

 

   

Ralf

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