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Hi all,
I wish to be able to modify a single bit within a bus from the Fabric using a PSoC4.
I found this post which (partly) answered my question : http://www.cypress.com/comment/142141#comment-142141
The problem is: the design won't generate with the attached schematic. You can notice I purposefully disconnected the wire [0], which goes through the OR gate.
The error code is: "Multiple drivers on signal "Net_43", bit(s) "0"."
Any idea on how to solve this?
Thanks!
Romain
Solved! Go to Solution.
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RomainF,
you can insert a "dummy" component to cheat the fitter. See example below which uses custom BusConnect component to do this:
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maybe so?
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Hi, thanks for the tip!
Basically I'd like this bit to be dependent on other logic. I managed to merge the bit [0] with a constant for the other bits [7:1].
That should do it for now for my use case. (see first image)
I tried to replicate this with a 2:1 mux without success. See second image below.
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odissey1 that did it!
Thanks for the help!
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