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PSoC™ Creator & Designer

misa_4395186
New Contributor

I am trying to create multiple clock dividers using the "Frequency Divider" component however I am quickly running out of UDB resources. Is there another way to divide an incoming signal in the KHz to multiple signals in Hz range without running out of space? I am using the CY8CKIT-043

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1 Solution
odissey1
Honored Contributor II

misa,

Attached is  a demo project, showing an input frequency divider operation in 1-shot mode and a Reset Timer to reload all timers once pulse burst is finished. Project includes PulseTrain generator component, which can be disabled if external pulse generator is available.

Note that maximum number of TCPWM dividers, that I was able to place on PSoC4200M is only 4 (out of total 8 available), with Error message "Not enough routing resources...", needs extra testing. Maybe you will be more lucky. Good news that UDB is practically free (if PulseTrain generator is disabled).

/odissey1

FreqDivider_01b_PulseGen.png.png

FreqDivider_01b_ResetTimer.png.png

FreqDivider_01b_Divider1_A.png.png

View solution in original post

13 Replies
Bob_Marlowe
Expert II

There are 8 (eight) TCPWM components in your PSoC4-M. They do not use UDBs.

Bob

misa_4395186
New Contributor

Hi Bob, The PWM component works but when I build, it errors with "the component requires a clock from the clock block" I believe this means that I can not feed in an external signal as an input for the clock. I am not sure how I can bypass this issue as the Frequency divider (UDB Component) did not have an issue feeding an external signal as my input clock...

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RodolfoGL
Employee

The frequency divider is not optimized to divide by a large number. It uses a registers, rather than the datapath. For instance, if you want to divide the frequency by 256, you would need to burn 8 macrocells. One UDB has only 16 macrocells.

If you use a datapath, you can have two frequency dividers (there are two accumulators in the datapath) that divides up to 256. So you could have frequency dividers based on UDBs and datapaths.

We don't have a frequency divider based on datapath, but perhaps someone in the community does.

Bob's suggestion also helps. You can use the TCPWM to count on the rising edge of your input signals, then use the TC to toggle your output signal. The divider is based on the period of the TCPWM.

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misa_4395186
New Contributor

Thanks for your input, if I do use the TCPWM to count as you described my input signal will only be used as a trigger to start the count. I was looking more for a divider application that is dependent on the input signal in a way that if my input frequency changes my output will also change.

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RodolfoGL
Employee

Not really. Setup the TCPWM to count on every rising edge and run continuously. On the TC event, the internal counter is re-loaded, so the TC event would occur periodically, which defines when your output signal toggles.

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odissey1
Honored Contributor II

misa,

The 7-bit downcounter (Count7) can be used as a divider (up to 128). Each consumes a Status register, which are not often used.

/odissey1

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RodolfoGL
Employee

Just a correction, the 7-bit counter (Count7) consumes a Control register. And it is indeed another method to implement the frequency divider with UDBs.

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misa_4395186
New Contributor

Ah hah finally got it working with a TCPWM (didn't realize that this block needs to be initiated in the code in order to run, newbie!). Now this counter is counting on the rising edge of my input signal (external clock), how can I generate a one time pulse once this input signal starts clocking and how do I kill and reset the counter once my input signal no longer clocking? I am guessing I can introduce another TCPWM with a one shot functionality instead of continuous for a trigger pulse, but not sure how to stop, reset, and have my counter wait until my input signal starts counting again! Thank you all for your help!!

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odissey1
Honored Contributor II

misa,

instead of going piecemeal, please describe of what your project is trying to achieve in general. This would help to better assisting you with a spectrum of solutions.

/odissey1

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misa_4395186
New Contributor

Odissey1,

Here's my project, I am feeding in an outside clock signal as my input signal that will be divided down into various output sync signals (I am using TCPWM component to do this), as soon as my input signal goes high I will need to generate a pulse on those output sync signals so they are all aligned once the input signal goes high. Finally if my input signal stop clocking, I will need to reset my TCPWM counters and set all my output sync signal low

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odissey1
Honored Contributor II

What is the frequency range of the input clock signal? What is interval between pulse trains? How many train packets per sec received? What is considered a timeout: a single clock missed or fixed time? What is duty cycle of the input clock signal?

/odissey1

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odissey1
Honored Contributor II

misa,

Attached is  a demo project, showing an input frequency divider operation in 1-shot mode and a Reset Timer to reload all timers once pulse burst is finished. Project includes PulseTrain generator component, which can be disabled if external pulse generator is available.

Note that maximum number of TCPWM dividers, that I was able to place on PSoC4200M is only 4 (out of total 8 available), with Error message "Not enough routing resources...", needs extra testing. Maybe you will be more lucky. Good news that UDB is practically free (if PulseTrain generator is disabled).

/odissey1

FreqDivider_01b_PulseGen.png.png

FreqDivider_01b_ResetTimer.png.png

FreqDivider_01b_Divider1_A.png.png

View solution in original post

misa_4395186
New Contributor

Thank you odissey1! Those are excellent building blocks that I can integrate into my project, I appreciate your help on this

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