Problem in ADC_SAR_Seq example project

[Anonymous]

DEVICE: CY8C5868AXI-LP035

   

I am using PSoC Creator 3.0 for my design and I was interested in SAR ADC component. In the example project of ADC_SAR_Seq there is a project in which four on-board (evaluation kit) VDACs give input to 4-channel SAR ADC and example projects helps to demonstrate that ADC can properly convert those voltages. I have mainly two problems with this:

   

1) I am using evaluation board. The Initial VDAC settings are 200 mV, 400 mV, 600 mV and 800 mV. The voltages, although, that are getting displayed on the LCD are 300, 600, 900 and 1200 mV respectively (readings of C1, C2, C3, C4). When I tried changing the VDAC settings to 300, 600, 900 and 1200, the voltages getting displayed on the screen are 450, 900, 1050 and 1800.

   

So is there a scaling factor of 1.5 somewhere which I am missing? The example project, I suppose should not behave like this, because I haven't made any kind of alterations inside the project.

   

2) When I faced above problem, I tried to replicate the exact project (with same pin numbers and configuration). I copied the exact same code from the project. When I tried to build it, it spewed out some errors that

   

a) Analog teminal "vdac_ref" on ADC_SAR_SEQ_v1_10 is unconnected (even though I have internally bypassed vdac_ref)

   

b) Analog terminal "AMuxHw_1.BoutTerm" on ADC_SAR_SEQ_v1_10 is unconnected.

   

Can someone please explain what is happening here? 

[ETRO_SSN583]

What board are you using ?

       

I recommend you post your project, use IE or Firefox to post.

           

"File"                      Creator

   

"Create Workspace Bundle"

       

Regards, Dana.

[Anonymous]

 Thanks for replying. Please find the bundle attached.

[Anonymous]

This is the original example project that I have posted here. I will post my own project soon.

   

Also even in the original project, the output on LCD should be

   

C1+0.20 C2+0.45

   

C3+0.59 C4+0.83

   

Instead of that it is displaying following. I have attached image of this.

[ETRO_SSN583 · Accepted solution]

I downloaded your project, and modified the code so it just loops in the section before you inc VDAC8 values.

       

I consistently get .2, .43, .64, .86 as readings. Thats for settings of 192 mV, 400 mV, 592 mV, 800 mV in the

   

respective VDAC8 properties.

       

The VDAC8 has a total G error of 5%, so readings within spec. Note I did not do an end to

   

end error analysis, for example VDAC8 output is not buffered, did not take into account Vref

   

error, offsets, etc..

       

So not sure what your issue is ?

       

Regards, Dana.

[ETRO_SSN583]

This API is for the last channel just converted, not the whole sequence, I believe.

       

ADC_SAR_Seq_IsEndConversion(ADC_SAR_Seq_WAIT_FOR_RESULT);

       

In order to flag the end of all channels being converted you need to use EOC and attach an ISR

   

component to it,set a flag in ISR. That will indicate -

       

eoc – Output

   

A rising edge on the end of conversion (eoc) output means that one conversion cycle is
complete. At this moment, conversion results for all channels are ready to be read from the
SRAM. An internal interrupt is also connected to this signal, or you may connect your own
interrupt.

       

Note you do not check for end of conversion for the incrementing case.

       

Regards, Dana.

[ETRO_SSN583]

Here is the implementation of ISR for SAR 4 channels conversion complete.

       

Attached.

       

Regards, Dana.

[Anonymous]

 Thanks a lot Dana. This helped me a lot.

   

Although when I programmed your project on my evaluation kit, it still displays initial VDAC settings as

   

C1+0.29 C2+0.61

   

C3+0.89 C4+1.21

       

There is a pattern here. Values on the screen are multiplied by 1.5

   

I am not sure what is the issue. Is there some setting on the hardware that I am missing?

   

I am using CY8CKIT-050 PSoC 5LP Development Kit with LP035 microcontroller.

[ETRO_SSN583]

I am using same kit.

       

I still do not understand where you see the 1.5 relationship. Below you

   

can see the BP I set, and results I get are .20, .43, .64, .86, which align with

   

the global proerties setting of each VDAC8 as stated earlier in this thread.