I am working on a design in Creator 3.0 using a PSOC5LP that uses internally generated 60MHz clock or clocks.
(3.7V on all Vdds and 0-85/125 temperature range.)
Occasionally the Static Timing Analysis, under Clock Summary says the maximum frequency for a certain clock is a NEGATIVE NUMBER!
What does this mean, other than it does not like the design?
PS: Is there a design recommendations document that addresses things like whether it is better to use one clock or multiple clocks of the same frequency? Or best methods for preventing hold time violations? I seem to get inconsistent or counter-intuitive results when I try simplifying my logic with the Static Timing Analysis.
Can you please provide us with an example showing your error? To do so, use
Creator->File->Create Workspace Bundle (minimal)
and attach the resulting file.
Thanks Bob, Dana. I will read thru that document again. I don't remember any info in there about one or multiple clock sources of the same frequency. Any thoughts there? Is it always better to use one clock source?
Attached is the timing report for an earlier version of a design I am doing for a client. As you can see, CyMASTER_CLK is negative.
Because my client does not want the design made public, I will try and produce a subset design that fails in the same way.
The current version of the design is down to one hold time violation of less than 0.4 ns and no frequency issues so I will probably go with that.
You can always file a CASE directly and Cypress will treat
all info as Proprietary -
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“Create a Case”
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