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PSoC™ Creator & Designer

Anonymous
Not applicable

I'm trying to use a shift register component in PSoC 4.   In order to probe the behaviour of the component I've set up this test setup to use control registers to test the shift register component.    The test code writes bytes into the FIFO and bitbangs the control signals.   

Capture1.PNG

The test pseudocode:

Write 0xa5 into the shift register 4 times

loop:

     write a count into the FIFO

     clock 8 bits through and check status.

     use the serial port to print the debug info to a console

Capture2.PNG

After the loop gets rolling it does seem to work, but I don't understand how to make the shift register output the bit's I want it to during the startup transient.  I'll probably have a similar problem when it comes time to go back into idle to wait for another burst of data.  Do I need to write a custom component with verilog?? 

My messy main program is attached:

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1 Solution
JobinT_31
Employee

HI,

In the main function, it seems some of the conditions given in datasheet is not met.

example:

ShiftReg_Start(void);

"Note that one component clock pulse is required to start the component logic after this function is called."

And there is no CyDelay given between xx_WriteData(), load/clock signals etc. This is required since the API calls, which is done by CPU will be very fast for Shift register to handle.

Use cystatus xx_WriteData() to check if the writedata is successful.

You can find a code example here: CE95372 - Shift register with PSoC 3/5LP | Cypress Semiconductor

Thanks

Jobin GT

View solution in original post

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1 Reply
JobinT_31
Employee

HI,

In the main function, it seems some of the conditions given in datasheet is not met.

example:

ShiftReg_Start(void);

"Note that one component clock pulse is required to start the component logic after this function is called."

And there is no CyDelay given between xx_WriteData(), load/clock signals etc. This is required since the API calls, which is done by CPU will be very fast for Shift register to handle.

Use cystatus xx_WriteData() to check if the writedata is successful.

You can find a code example here: CE95372 - Shift register with PSoC 3/5LP | Cypress Semiconductor

Thanks

Jobin GT

View solution in original post

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