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I'm trying to use a shift register component in PSoC 4. In order to probe the behaviour of the component I've set up this test setup to use control registers to test the shift register component. The test code writes bytes into the FIFO and bitbangs the control signals.
The test pseudocode:
Write 0xa5 into the shift register 4 times
write a count into the FIFO
clock 8 bits through and check status.
use the serial port to print the debug info to a console
After the loop gets rolling it does seem to work, but I don't understand how to make the shift register output the bit's I want it to during the startup transient. I'll probably have a similar problem when it comes time to go back into idle to wait for another burst of data. Do I need to write a custom component with verilog??