I am trying to use a Sample and hold component to hold constant a voltage in a circuit at certain times. The time period to hold the voltage isn't repetitive and is controlled from the API C code.
I tried doing this by setting the Sample and hold block "Sample clock edge" to "Negative" and the 'Sample mode" to "Sample and Hold".
I can't use use a clock entrance for "sclk" because I don't want to sample in a repetitive interval. For the sclk input I created a logical control signal that is logical high before I need to hold the signal and is changed to logical low when I need to to Hold constant a new Value from the Vin input.
This process repeats itself using a code loop that set the logical control signal to '1' in the beginning of each loop iteration
Unfortunately this doesn't seem to work and the Sample and Hold output seems to be stuck at a voltage close to 0V.
Do you have Any Idea how should I use the Sample and hold Component so that it would work properly?
Solved! Go to Solution.
Thanks, It seems to work fine.
Do you know what is the droop rate that I should be expecting?
You can always use a A/D to effect a S/H, no droop issues. Especially effective
in applications that need very long hold times, no special low leakage caps
needed (for S/H).
You can also effect a long term S/H with analog mux and an OpAmp on in and out
of mux, and a cap of your choosing.
I looked at component datasheet, droop rate spec shown w/o an entry.
You could always set up DelSig and measure it, or file a CASE and ask
for the spec.
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