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MK22
Level 1
First reply posted First question asked Welcome!
Level 1

Hi there,

I'm trying to make a custom component written in Verilog which uses a Control Register and Status Register for interacting with C firmware. However, the API for both the status and control registers aren't generated, but I've noticed this is not an issue when using the UDB Editor instead? I've included an example project which showcases the issue with the Control Register, the same happens when a Status Register is instantiated in the component's verilog (the status register API shown below is from the TopDesign schematic, not the custom component).

As shown below, the component contains a control register but the associated API is not generated.

MK22_0-1643084558559.png

MK22_1-1643084578675.png

I'm using PSoC Creator 4.4 and the target device is a PSoC 3.


Also, not quite related, but for the status and control registers there seems to be no include guard for either registers so they get defined multiple times if there are multiple components using them (or in the TopDesign)? I've gotten around this by removing the includes in my verilog when necessary. Is there an existing macro defined somewhere to ifndef the includes with in my own verilog files?

Thanks in advance!

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1 Solution
Ekta
Moderator
Moderator 250 sign-ins First question asked 500 replies posted
Moderator

Hi @MK22 

I guess the observation made by you is valid. This is because when you are using a UDB Editor to add a control or status register it uses the Status and Control register component by Cypress. 

If you drag and drop a control register component on your top design and build the project then you would notice that the same set of .c and .h files are generated. The UDB Editor guide also mentions the same.

Ekta_0-1643296980739.png

However, in your project in the Verilog file for the custom component, you have created I observed that you have included only the .v file for the control register library. So the .c and .h files would not be generated.

Kindly let me know in case of any clarifications or if my understanding of the issue is not correct.

Best Regards
Ekta

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3 Replies
Ekta
Moderator
Moderator 250 sign-ins First question asked 500 replies posted
Moderator

Hi @MK22 

I guess the observation made by you is valid. This is because when you are using a UDB Editor to add a control or status register it uses the Status and Control register component by Cypress. 

If you drag and drop a control register component on your top design and build the project then you would notice that the same set of .c and .h files are generated. The UDB Editor guide also mentions the same.

Ekta_0-1643296980739.png

However, in your project in the Verilog file for the custom component, you have created I observed that you have included only the .v file for the control register library. So the .c and .h files would not be generated.

Kindly let me know in case of any clarifications or if my understanding of the issue is not correct.

Best Regards
Ekta

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MK22
Level 1
First reply posted First question asked Welcome!
Level 1

Hi @Ekta , 

Thanks for the reply!

Sorry, I forgot to mention that the compiler errors about multiple definitions when you have multiple control/status registers, as they are included twice. Are multiple control/status registers not possible with a PSoC?

As for the component, I don't quite get what you mean by I've only included the .v file? I just copied the autogenerated verilog from the UDB Editor as a template, including the verilog include. Are there other files I need to include? If so, how do I know which ones?

Thanks
MK

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Ekta
Moderator
Moderator 250 sign-ins First question asked 500 replies posted
Moderator

Hi @MK22 

What I meant was that, when you are using the UDB editor, the editor directly uses the UDB based components control register and status register and generates the source files for these compoenents(.c and .h files associated with this component which contains the APIs for using the component)

If you import a status register or control register in your project then under the components tab in the workspace explorer you can see that by default the status and control registers contain a lot of other files (like the verilog file) apart from the .c/.h files.

Ekta_0-1648626907075.png

 

But when you are trying to create a component of your own using only the verilog file and the symbol file the APIs are not generated.

Ekta_1-1648626938360.png

In the component01 you have created in you project you have included the path to the verilog file of the control register as can be sen in the image below:

Ekta_2-1648627123994.png

You can add .c and .h files to your project by right clicking on the component created (under compoents Tab) > Selecting API C file or API Header file

Ekta_3-1648627273468.png

Best Regards
Ekta




 

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