PSoC™ 6 Forum Discussions
Per our previous discussion: PSOC6: CY8C6247BZI-D54 Pin out
-->The decision was made to use the PSOC 6 MCU CY8C624ABZI-D44 Instead of the CY8C6247BZI-D44. Thank you for your help in helping me persuade my customer to take that huge improvement now instead of later.
Overview:
I received the CY8CPROTO-062-4343W PSoC 6 Wi-Fi BT PROTOTYPING KIT. This kit contains a CY8C624ABZI-S2D44ES2 1943 B 33 CYP 636440 W3A633
1. Is this the latest chip with latest firmware?
Development:
2. I am not able to load the CY8CPROTO-062-4343W kit with wiced IDE, having read forums its my understanding that only modustoolbox may be used. Is that correct?
3. From reading the forums it appears that mbed is preferred and recommended for AWS IoT. Is that correct?
4. If 3. is correct, Then does Cypress recommend and provide a cypress-mbed like they do a cypress-freertos?
5. If available, which cypress provided mbed-application(s) is recommended to use as a base for my AWS IOT development? I need mqtt, tls, tcpip, and stuff I dont know I need 😕
Show LessHi All,
I have two projects using the PSOC 63 (CYBLE-416045-02) modules, as Central and Peripheral.
Both devices use Dual Core BLE, Controller on CM0+ and Host on CM4.
Peripheral is a battery operated device and must use DeepSleep when not active.
I have ran extensive testing (~120hrs continuous) on the communications keeping the Peripheral "awake", and unable to reproduce the issue.
Peripheral handles incoming data (write without response from central) from BLE AppCallBack, and sends Notification right the way with data already available.
What is happening:
- Communication runs fine (7.5ms intervals, 3x16byte packets every 8ms + 16byte every 1sec) in DeepSleep for seemingly random periods
- Anywhere between 5mins - 5hrs after, the Peripheral BLE Stack or Controller hangs somehow
- Central Stack stays CY_BLE_STACK_STATE_BUSY, and will not become FREE, unless I issue Cy_BLE_GAP_Disconnect(), to get back to "Scanning State"
- Peripheral still thinks it is connected, and CM4 goes on doing it's 500ms supervisory tasks in DeepSleep.
- Peripheral functions fine for the rest of the code, I can wake it up, go back to sleep again, and manually trigger BLE operations that fail.
- Attaching to CM0+ Controller core shows nothing suspicious, it only has Cy_BLE_ProcessEvents() and Cy_SysPm_CpuEnterDeepSleep(CY_SYSPM_WAIT_FOR_INTERRUPT), breakpoints here are constantly hit.
After Peripheral hangs, I tried:
- Send Notification - After about 2-3 notifications peripheral reports "CY_BLE_STACK_STATE_BUSY" and stays that way
- Cy_BLE_GAP_Disconnect() reports CY_BLE_ERROR_INSUFFICIENT_RESOURCES every time
Some of the things I tried to narrow things down and help the issue, with no luck:
- Increased Stack and Heap size on peripheral to 1600/1600 and 800/800 on Central
- Disabled debugging printf() on peripheral
- All kinds of ways and places to process received data, process data to be transmitted, call Cy_BLE_ProcessEvents(), Interrupt priorities
Anyone has encountered similar problems in DeepSleep?
How can I effectively debug what is happening under the hood of the BLE component?
Any way to recover from such a state?
Any pointers would be greatly appreciated.
Regards,
Adam
Show LessHello.
Below link has sample projects for Broadcaster and Observer on PSoC4.(Day008 and Day010)
https://github.com/cypresssemiconductorco/PSoC-4-BLE/tree/master/100_Projects_in_100_Days
Are there similar simple PSoC6 sample projects for Broadcaster and Observer?
Best Regards.
Yutaka Matsubara
Show LessI've put a lot of effort into reducing the attached design's appetite for MCs and PTs from >80% to below 50%. However, as soon as I add the 17th timer to the top-level design, routing fails. Why? And how can I proceed?
Show LessI will be using the PSoC 6 to store a firmware image to then program other PSoCs. For now I just want to store 512kB of data on its internal flash.
I went through the PSoC6 MCU Basic Device Firmware Update document(CE213903) and that found I could store about 256kB onto its internal flash, but higher than that I run into problems. I am just using cy_flash.h, specifically Cy_Flash_EraseRow and Cy_Flash_ProgramRow to store my data.
From the Memory layout in CE213903 it appears 128kB are sectioned off for app1 core0, and app1 core 1. I want to increase this size to be 512kB, but I am not sure what to change in the linker files(dfu_cm4.ld, and dfu_cm0.ld) to increase the memory sectioned off. The memory map shows that there are 639kB starting at 0x1006 0000 that are empty/reserved so I am hoping to use that.
Does anyone know how to modify those linker files to allow me access to 512kB of memory?
Show LessI have the PSoC 6 connected to four MX25(https://www.macronix.com/Lists/Datasheet/Attachments/7534/MX25R3235F,%20Wide%20Range,%2032Mb,%20v1.6.pdf )external flash chips over SPI.
When I connect any one, or two chips to the psoc I can read and write great. When I connect 3 or more I am unable to read or write any data to any of them. Everything shows up incorrectly.
Any idea what could be causing this? I have tried adding pull up resistors to the chip selects. Also all of the chips work separately, and work in any combination of two.
Show LessHi,
I'm trying to use 400kbps as desired data rate for my I2C component, but only to discover that the SCB clock (kHz) generated by PSoC Creator itself is set to 7500, which apparently to be out of range. Is there anyway to help understand how this clock value is generated while I'm not using external clock terminal?
Thanks!
Best,
Joseph
Show LessAre there specific DC-DC power interface or ESD protection circuits from Infineon that pair well with PSoC 6?
I'm interested in design examples or reference designs that pair PSoC 6 with Infineon power components or sensors.
Greg
Show LessI'm trying to achieve the following:
One component in my design outputs a trigger signal. On each positive edge of this output, I'd like use one DMA channel to do the following things:
- Transfer one halfword from the SAR ADC to a 16-bit UDB
- Transfer one word from a timer to a memory location (uint32_t)
- when both are done, the DMA channel should generate one output trigger that is routed into the UDB.
I connected the DMA channel's trigger input and output to a scope. I can see the input triggers, but the output is silent. These are my descriptors:
My guess is that, since descr_timer is chained back to descr_adc, an endless loop is created and no trigger is generated because the entire (endless) chain is never completed. However, I've tried many other combinations of settings and none of them had the desired result.
I've also attached the current state of the whole project (the DMA component in question is in the top level design).
I'm thinking about handling DMA errors with the DMA's interrupt. It would be triggered only on errors, not on channel completion. Any advice on this is appreciated, but not the main point of this question.
Show Less