PSoC™ 6 Forum Discussions
There were rumours about PSoC 7 family. Are we any closer to see the introduction of that family ? On our side, we are in the process of new product development. We would need all that great functionality together with the full 1.8V to 5.5V operation, 24+ UDB and plenty of analogue. Can we expect something like that ? And may be HS USB as well....
Show LessMy supervisor wants to get all of our firmware into the Keil uVision environment. I am willing to do it but how to I generate and edit the Peripherals such as BLE, SPI and Timers without the Topdesign schematic capture? or do you have a plugin for Keil uVision. is there a non graphical or another way to generate the low level firmware files?
Current IDE version: PSOC creator 4.2
OS: windows 10
moving to: Keil uVision 5.34.0.0
MCU: cyble-416045-02
thanks
Show LessWhile attempting to program a CY8CKIT-064S0S2-4343W with AWS_Demo;
The project appears to build successfully.
After build, the programming stops after "Using CMSIS loader" line and
Before CMSIS-DAP: SWD Supported line.
When the programming stops, the kit resets, and reverts back to the previous program loaded.
These are the only lines that show up in the Console:
=================================
Open On-Chip Debugger 0.10.0+dev-4.1.0.1058 (2020-08-11-03:47)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
** Main Flash size limited to 0x1D0000 bytes
adapter speed: 2000 kHz
adapter srst delay: 0
adapter srst pulse_width: 5
Info : auto-selecting first available session transport "swd". To override use 'transport select <transport>'.
** Using POWERUP_DELAY: 5000 ms
** Using TARGET_AP: cm0_ap
** Using ACQUIRE_TIMEOUT: 15000 ms
Info : Using CMSIS loader 'CY8C6xxA_SMIF_S25FL512S' for bank 'psoc64_smif_cm0' (footprint 15180 bytes)
srst_only separate srst_gates_jtag srst_open_drain connect_deassert_srst
=======================================
What could cause this issue?
Are there additional log files to check or other examples to try?
The board is provisioned with the same security that was used to create the project.
Greg
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I was more than interested to see the video concerning ModusToolbox. The videos are good on what they cover. What the first video does not cover bothers me.
One glaring omission in the first video was the ability to add your own custom designed logic (via UDB manipulation) to the PSOC6, either visually or through code (i.e. Verilog). In the Cypress Creator, it is possible to do either Visual design with the IP Toolbox on pre-crafted components, or using Verilog for the PSOC 6.2 and below (PSOC5, PSOC4, PSOC3). They did mention 3rd party designs, but there was no hint you could create your own IP.
Since, according to video #1, all new PSOC products will be supported only by the ModusToolbox, is this a signal that Cypress will no longer support the custom logic design methodology? Are they removing UDB's from future products? If they are supporting custom design, will it be visual, or just code. If code, will the magic incantation be published?
If no custom logic design is supported, I am very disappointed. It removes future versions of PSOC6 from strong consideration for new products, at least for me. I will stick with PSOC 6.2 (still supported by PSOC Creator) or below. PSOC5 works well for us, due to being CMOS, and it works at very high temperatures (needed for automotive and Oil Field.)
Show LessHi, there. I'm using the CY8CKIT-062-BLE and thought about interfacing with a character LCD for debugging purposes. I was thinking about implementing an ad hoc solution, but then I found that there is a LCD Component. However, it does not appear in my component catalog (it's not under Display or anywhere else). I tried Tools > Find new components, but couldn't find it either.
Any help would be welcome. Thank you.
Júlio Tanomaru, Brazil
Show LessI have a PSoC 6.3 Pioneer Kit (HW REV 11) and am having trouble running any of my own (or example) programs on the PSoC.
I have the latest PSoC Creator (V4.4) installed with PDL V3.1.4 and the latest KitProg firmware update (Firmware version 2.10.878). I just created a new example project in PSoC Creator of the DualCoreBlinky application and compiled an ran it. It compiles just fine, and seems to program just fine, but nothing happens on the board (no blinking LED). I confirmed that the KitProg light blinks momentarily while it is uploading the firmware so it *seems* that the board is responding. no noticeable errors on PSoC Creator.
To troubleshoot, I tried running the debugger with a breakpoint set at the beginning of the Main function of the M0+ core. When I set the Target to the M0+ and hit debug, It never goes to the breakpoint. When I hit the pause button. I'm dropped into a disassembly somewhere and if I press the step into or step over buttons, nothing changes. If I press the step out button, I get the error: "The run request failed. Encountered error (Warning: Cannot insert breakpoint 0. Cannot access memory at address 0x160022a6 )"
I also tried making my own blank program on the CM0+ core to blink the LED with the following code inside the for loop for the CM0+ core:
/* Place your application code here. */
Cy_GPIO_Write(LED_0_PORT, LED_0_NUM, 1);
CyDelay(500);
Cy_GPIO_Write(LED_0_PORT, LED_0_NUM, 0);
CyDelay(500);
NOTE: I created a digital pin in the schematic called LED and connected it to Pin 0[3] on the chip.
But again, the same problem. It programs fine but nothing happens, and I can't step through the code. Any idea what is going on? I'm hitting a brick wall here so far.
Thanks,
Jason O
Show LessHello All,
I am currently working on a dual application project that uses a different top design. I haven't been able to find any documentation that states how the logic/UDB/mesh/GPIO works when switching from one app to another. I have searched through the psoc 63 TRM and the 3.1.2 pdl documentation and came up unsuccessful. My questions are:
How does the reprogramming of UDB and logic work when using a dual application project? Does it initialize the mesh when app0 starts and then that UDB and GPIO configurations is locked for app 1? Or is each component re-routed when app1 in flash is started?
Thanks!
Show LessI have a custom UTF8S string characteristic that I've configured for 32 bytes in my projects' BLE PDL. Using CySmart, attempting to write a string having greater than 20 bytes will silently fail. I tried increasing the MTU size to 50 from 23 and the LL max Rx/Tx payload sizes to 100 from 27 and I still hit the same 20 byte limit. Can someone please tell me how to successfully write string characteristics having greater than 20 bytes?
Show LessHi,
I have successfully created my own BSP in ModusToolbox.
But when I tried to add custom memory configuration using QSPI Configurator tool I faced the issue: The new project is created and even built successfully with custom BSP on other PC, but if I open the QSPI Configurator it throws the error that APS6404L-3SQR-ZR.cymem file is empty. And I have to re select the file and configure all the memories all over again.
So what wold be correct way to include the *.cymem files into the custom BSP project?
I have attached the Custom BSP project (it is for CY8C6245AZI-S3D72 custom board)
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