PSoC™ 6 Forum Discussions
I'm running a system that has a BLE stack running on the CM0+ core and a main application running on the CM4 core. The main application needs to be able to put both cores into sleep mode. I suppose I have to set up some form of inter-core communications and send a request from CM4 side to the CM0+ side requesting the CM0 core put itself to sleep. Anybody have a recommendation/example of how to do that? And how to wake up the CM0 core once the CM4 core wakes up on an interrupt?
Thanks,
Ed H.
Show LessHi
Using the I2C low-level API allows to catch errors including: CY_SCB_I2C_MASTER_MANUAL_ADDR_NAK and others.
Yet, these are not available in the high-level API.
Is there a work around ?
I am trying to scan for I2C slaves using high-level APIs, but I couldn't find a way to check for missing slaves.
thanks
Show LessHi,
Is the processor vulnerable to the Braktooth vulnerability? Also, is moving to the BT SDK 3.2, available in late Q4 2021, have any other security or other advantages?
Show LessHi,
I am trying to read a voltage value from a Input Pin and using an ADC; I want to send the value via BLE to the Mobile Application.
Can you please help me with some example how to do that?
Show LessHi,
I am working on PSOC 6 PROTO 062 4343W development board. I am trying to read and write into external flash present on development board. I am using ModusToolbox as IDE. Initially I downloaded sample example code of QSPI XIP, and now I am trying to the same thing but without using serial flash library .
So I initialized smif by using smif functions, then I tried to read and write into memory in command mode by using smif functions, which is working fine. Now I want to read the data from FLASH in XIP mode, so I changed the mode to XIP. Then as the documentation says we can not use smif functions in XIP mode, I am writing into flash with a variable declared as follow,
const char *hi_word CY_SECTION(".cy_xip") __attribute__((used)) = "Hello from the external string!\n";
Now, in the linker script all the sections are declared. I am using the same linker script generated with sample QSPI XIP example code. I have made the necessary changes in my makefile. There is one preprocessing directive named CY_ENABLE_XIP_PROGRAM which I have mentioned in my makefile and also defined this directive as follow,
In Makefile : in Makefile : DEFINES=CY_RETARGET_IO_CONVERT_LF_TO_CRLF CY_ENABLE_XIP_PROGRAM
In source file :
#if defined(CY_ENABLE_XIP_PROGRAM)
#include "cycfg_qspi_memslot.h"
typedef struct
{
const cy_stc_smif_block_config_t* smifCfg; // Pointer to SMIF top-level configuration
const uint32_t null_t; // NULL termination
} stc_smif_ipblocks_arr_t;
// This data can be placed anywhere in the internal memory, but it must be at a location that
// can be determined and used for the calculation of the CRC16 checksum in the cyToc below. There
// are multiple ways this can be accomplished including:
// 1) Placing it in a dedicated memory block with a known address. (as done here)
// 2) Placing it at an absolute location via a the linker script
// 3) Using 'cymcuelftool -S' to recompute the checksum and patch the elf file after linking
CY_SECTION(".cy_sflash_user_data") __attribute__((used))
const stc_smif_ipblocks_arr_t smifIpBlocksArr = { &smifBlockConfig, 0x00000000 };
// This data is used to populate the table of contents part 2. When present, it is used by the boot
// process and programming tools to determine key characteristics about the memory usage including
// where the boot process should start the application from and what external memories are connected
// (if any). This must consume a full row of flash memory row. The last entry is a checksum of the
// other values in the ToC which must be updated if any other value changes. This can be done
// manually or by running 'cymcuelftool -S' to recompute the checksum.
CY_SECTION(".cy_toc_part2") __attribute__((used))
const uint32_t cyToc[128] =
{
0x200-4, // Offset=0x0000: Object Size, bytes
0x01211220, // Offset=0x0004: Magic Number (TOC Part 2, ID)
0, // Offset=0x0008: Key Storage Address
(int)&smifIpBlocksArr, // Offset=0x000C: This points to a null terminated array of SMIF
// structures.
0x10000000u, // Offset=0x0010: App image start address
// Offset=0x0014-0x01F7: Reserved
[126] = 0x000002C2, // Offset=0x01
// Bits[ 1: 0] CLOCK_CONFIG (0=8MHz, 1=25MHz, 2=50MHz, 3=100MHz)
// Bits[ 4: 2] LISTEN_WINDOW (0=20ms, 1=10ms, 2=1ms, 3=0ms, 4=100ms)
// Bits[ 6: 5] SWJ_PINS_CTL (0/1/3=Disable SWJ, 2=Enable SWJ)
// Bits[ 8: 7] APP_AUTHENTICATION (0/2/3=Enable, 1=Disable)
// Bits[10: 9] FB_BOOTLOADER_CTL: UNUSED
[127] = 0x3BB30000 // Offset=0x01FC: CRC16-CCITT
// (the upper 2 bytes contain the CRC and the lower 2 bytes are 0)
};
#endif // defined(CY_ENABLE_XIP_PROGRAM)
I have done all this by referring to the document AN228740. So now flash is configured and flash will be written during programming , I want to read the variable and I am doing that as follow,
/* Set XIP mode */
Cy_SMIF_SetMode(SMIF0, CY_SMIF_MEMORY);
Cy_SMIF_Enable(SMIF0, &smifContext);
addr = (uint32_t)&hi_word;
SendStringToUart(hi_word);
But the problem I found during debugging is, the hi_word varible is getting declared at base FLASH memory location i.e. 0x18000000 but there is no data written at that location. and because of that no data is being read.
As per the document AN228740 I have followed all the steps but it is not working and now I dont know where I am wrong.
Can you please help ?
Regards
Rushikesh
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PSoC6. How to excute FW in SFlash by XIP and write log data or file system in SFlash?
For write data in SFlash we need disable XIP. so it is conflict when excute FW in SFlash.
Is there a walkaround way, I am looking some sample code.
Thanks!
Max
Show LessI am trying to run the "BLE_FIND_ME" program on my CY8CKIT-062-BLE, P63 device.
Tried Creator and Modus getting the same failure: for Creator (V4.4) it is “can't open cmsis-dap port” for Modus (Version: 2.3.0 Eclipse Build ID: 2307) it is “Error: kitprog3: failed to acquire the device”
Updated the kitprog to the latest version:
Info : CMSIS-DAP: SWD Supported
Info : CMSIS-DAP: FW Version = 2.0.0
Info : CMSIS-DAP: Interface Initialised (SWD)
Info : SWCLK/TCK = 1 SWDIO/TMS = 1 TDI = 0 TDO = 0 nTRST = 0 nRESET = 1
Info : CMSIS-DAP: Interface ready
Info : KitProg3: FW version: 2.21.1005
Info : KitProg3: Pipelined transfers enabled
Info : VTarget = 1.798 V
Still have the same problem, this kit has worked in the past.
Thanks
Show LessWhen you setup BLE on 2 cores,
in core M0+, it has these 2 functions:
"Cy_BLE_Start(0)" and "Cy_BLE_ProcessEvents()" as follows:
int main(void)
{
__enable_irq(); /* Enable global interrupts. */
Cy_BLE_Start(0);
Cy_SysEnableCM4(CY_CORTEX_M4_APPL_ADDR);
for(;;)
{
Cy_BLE_ProcessEvents();
}
}
These 2 functions are redundant in CM4, where they are called as follows:
Cy_BLE_Start(genericEventHandler);
for(;;)
{
Cy_BLE_ProcessEvents();
}
The questions are:
-Why we redundantly call the functions from 2 cores ?
-If I need to run BLE without interrupting its service, while i need to loop other tasks, without using RTOS. What is the efficient method to use ? for example if I need to run the BLE on one core, and other tasks on another core, i need to send data by BLE. How can I trigger the BLE for data transfer ? can I use an interrupt across the 2 cores ? i don't think IPC supports transferring interrupts
thanks
Show LessHello,
Question:What is the meaning of “Total Internal SRAM (Available) 1046528”
As the picture shows :
SRAM SIZE:1MB
Note:that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use.
SRAM The biggest theory :1024*1024=1048576(byte)
SRAM Actual maximum :1048576-2176=1046400(byte)
But,“Total Internal SRAM (Available) 1046528 ”
1046528-1046400=128(byte)
Where did this 128 bytes come from?
注:
best wishes,
JCD
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