Hello,
I have started a project from the PDM to I2S example ( https://github.com/Infineon/mtb-example-psoc6-pdm-to-i2s ) in which I have developed an ...
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Hello,
I have started a project from the PDM to I2S example ( https://github.com/Infineon/mtb-example-psoc6-pdm-to-i2s ) in which I have developed an audio bypass system (to later implement our audio processing system on it) instead of the recording-playing app.
So far I have achieved this goal at a sampling rate of 8 KHz. I need to use a sampling rate of 16 kHz. Changing the MCLK value for the audio codec and the sampling rate define to 16 kHz effectively changes the sampling rate, however, it makes appear undesired harmonics in the higher frequencies. I tried playing a sinusoid of 2400 Hz directly from the mcu to the codec and it also creates these harmonics, as in the attatched spectogram screenshot. I also attatch the screenshot at 8 kHz.
My configuration is the following:
i2s is master, codec working in EXT slave mode with 256fs (same as the example)
/* Master Clock (MCLK) Frequency for the audio codec */
//#define MCLK_FREQ_HZ 2041000 /* for 8 kHz */
#define MCLK_FREQ_HZ 4096000 /*for 16 kHz */
/* Duty cycle for the MCLK PWM */
#define MCLK_DUTY_CYCLE 50.0f /* in % */
/* Desired Sample Rate */
#define SAMPLE_RATE_HZ 16000u
/* Decimation Rate of the PDM/PCM block */
// sinc rate = decimation rate / 2
#define DECIMATION_RATE 64u
/* Clock Settings */
#define AUDIO_SYS_CLOCK_HZ 98000000u /* in Hz. Ideally 98.304 MHz */
/* HFCLK1 Clock Divider */
#define HFCLK1_CLK_DIVIDER 4u
/* ... */
const cyhal_i2s_config_t i2s_config = {
.is_tx_slave = false, /* TX is Master */
.is_rx_slave = false, /* RX not used */
.mclk_hz = 0, /* External MCLK not used */
.channel_length = 32, /* In bits */
.word_length = 16, /* In bits */
.sample_rate_hz = SAMPLE_RATE_HZ, /* In Hz */
};
const cyhal_pdm_pcm_cfg_t pdm_pcm_cfg =
{
.sample_rate = SAMPLE_RATE_HZ,
.decimation_rate = DECIMATION_RATE,
.mode = CYHAL_PDM_PCM_MODE_STEREO,
.word_length = 16, /* bits */
.left_gain = CYHAL_PDM_PCM_MAX_GAIN, /* dB */
.right_gain = CYHAL_PDM_PCM_MAX_GAIN, /* dB */
};
/* ... */
clock_init();
/* Initialize the Master Clock with a PWM */
cyhal_pwm_init(&mclk_pwm, MCLK_PIN, NULL);
cyhal_pwm_set_duty_cycle(&mclk_pwm, MCLK_DUTY_CYCLE, MCLK_FREQ_HZ);
cyhal_pwm_start(&mclk_pwm);
/* Initialize the I2S */
cyhal_i2s_init(&i2s, &i2s_pins, NULL, NC, &i2s_config, &audio_clock);
//cyhal_i2s_register_callback(&i2s, i2s_isr_handler, NULL);
cyhal_i2s_register_callback(&i2s, i2s_callback, NULL);
cyhal_i2s_enable_event(&i2s, CYHAL_I2S_ASYNC_TX_COMPLETE, CYHAL_ISR_PRIORITY_DEFAULT, true);
/* Initialize the PDM/PCM block */
cyhal_pdm_pcm_init(&pdm_pcm, PDM_DATA, PDM_CLK, &audio_clock, &pdm_pcm_cfg);
cyhal_pdm_pcm_register_callback(&pdm_pcm, &pdm_pcm_callback, &pdm_pcm);
cyhal_pdm_pcm_enable_event(&pdm_pcm, CYHAL_PDM_PCM_ASYNC_COMPLETE, CYHAL_ISR_PRIORITY_DEFAULT, true);
#ifdef USE_AK4954A
/* Initialize the I2C Master */
cyhal_i2c_init(&mi2c, CYBSP_I2C_SDA, CYBSP_I2C_SCL, NULL);
cyhal_i2c_configure(&mi2c, &mi2c_config);
/* Configure the AK494A codec and enable it */
result = mtb_ak4954a_init(&mi2c);
/* If the initialization fails, reset the device */
if (result != 0)
{
NVIC_SystemReset();
}
mtb_ak4954a_activate();
// mtb_ak4954a_set(AK4954A_REG_PWR_MGMT2, 0x08);
mtb_ak4954a_adjust_volume(AK4954A_HP_VOLUME_DEFAULT);
//mtb_ak4954a_write_byte(AK4954A_REG_MODE_CTRL2, AK4954A_MODE_CTRL2_CM_512fs | AK4954A_MODE_CTRL2_FS_32kHz);
#endif
I'm not sure but may it have anything to do with the pwm generated clock? Any help would be appreciated.
Thank you
jp
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Jan 27, 2022
Solved
