PSoC™ 6 Forum Discussions
Hi,
while porting WHD, I have similar question as https://community.infineon.com/t5/Wi-Fi-Combo/Support-for-porting-WHD-to-stm32F7/m-p/212755 .
1. However this question seems not answered fully. So, please let us know it.
2. & I assume the port specific type can be something like below -
e.g.
I setup the PSoC 62S4 Kit ADC , with 2 channels as singled end, Vref=VDDA, Vminus=VSSA. When feed the Vplus with known signal (or voltage) , the voltage readings of the two channel is ok and as expected. When I disconnected the signal, i.e. the Vplus open ended, I got reading (as calculated) is fixed as 2.8V . Is this normal? As I thought an open-ended Vplus will get varying readings from time to time, or at least the level is not so high.
Show LessHello Infineon Support,
Apologies, I originally posted about this issue here, but I was taken off the project before I was able to test it out. I'm back on now and I'm still getting this error after the BLE stack is initialized:
hci_open(): init error (0x4021c00)
The old post wouldn't let me reply so I'm adding some information here.
First off, I can confirm that I have the most up-to-date version of the BSP and libraries available, so that is not the issue.
Second, I'm using the Bluetooth_LE_CapSense_Buttons_and_Slider project as a baseline, and when I run that project, it works as expected and I do not get the HCI error.
For my project, I copied in the ble_task files and the design.cybt file, so my setup should be the same for all the bluetooth libraries and functions. I confirmed that my Makefile has the FREERTOS and WICED_BLE components added to it.
There's two other notable differences between my project and the original capsense project:
- My project is a dual core project, with a smaller app running on CM0P
- My project has some WiFi libraries it is using
Could either of those differences cause contention issues with the HCI hardware? I've tried all sorts of things to get this running but cannot shake this error message.
Best regards,
Cory
Show LessHi.
The most recent discussion on this topic dates back to 2018. At that point, Cypress did not support running FreeRTOS on the PSoC 6's CM0+ core.
First - has that position changed? Is there any official support for FreeRTOS on the CM0+?
Second - has anyone done this, especially using ModusToolbox? If so, would you please share your experience here?
A side issue is that the procedure for developing dual-CPU applications using ModusToolbox omits the FreeRTOS include directories from the compiler command line. The obvious brute-force workaround would be to add them in the CM0+ Makefile. Is there a better way?
There is a CM0 port of FreeRTOS available directly from FreeRTOS - download the FreeRTOS distro, then look in
<distro root>/FreeRTOS/Source/portable/<compiler>/ARM_CM0
The port is not specific to the PSoC 6, of course, and I'm unclear exactly what, if anything, needs to be changed.
For background, we plan to run FreeRTOS on both PSoC 6 cores. The CM0+ will handle data acquisition code (external multi-channel SPI ADC via DMA), and lightweight feature detection. The CM4 will be called into action for heavyweight processing when a feature is detected.
Thanks,
-Nick
Show LessHi Community,
Hope you are good. Did anyone has example of any temperature sensor with it's .c file written in freertos?
I am trying to write it but facing a problem. Can anyone help me on this ?
Regards,
Ali Shoaib
Show LessHey,
We are using PSOC6 CY8C6347BZI-BLD53 for our product. I am trying to add additional timer counter blocks (tcpwm) which will bring our in project use to 27 timers. The chip has 32 blocks available. I get this error upon enabling the 23rd timer block
E2810: The solution search limit for pin and fixed function block placement has been exceeded.
Attaching a screenshot for the full error. When I only have 22 timers, the error goes away so I know it is the TCPWM block and no other components.
Is there a way to know if the other blocks are used elsewhere internally? We have BLE enabled alongwith several other blocks including wdt, spi, i2c, uart etc.
Thanks in advance,
Vandita
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Hello,
I am using PSoC 6 PROTO kit. I am trying to achieve synchronization in between two cores by using semaphores and sharing single UART port in two cores, CM4 and CM0+. I am getting a slight issue in the output. I checked with semaphore example provided by cypress then I created a empty project for dual core. With the help of Device Configurator I initialized the UART port and User LED on the board.
Same as "Semaphore Example" I am trying to send data to UART from both cores. But the project I created it shows some discrepancy. CM4 UART gets executed twice and CM0+ UART for once8[CM4 CM4, CM0+, CM4 CM4], whereas the output should be [CM4 , CM0+, CM4]. Please refer to attached output image.
The project I created is same as example project, I checked the clock is also same. but not getting why I am getting expected output. Need your help in understanding. As far as concept is concerned it is able to synchronize the shared resource, but not able to understand discrepancy in the output.
Thanks
Rushikesh
Show LessI'm attempting to load the Setup Package for CY8CKIT062WiFiBT
DOWNLOAD - CY8CKIT062WiFiBTSetupOnlyPackage_RevSS.exe
The process stops with a note that the PDL 3.0 is missing
I have PDL 3.1 loaded.
The "Download" button for PDL 3.0 sends me to a 401 error - page not found
Greg
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I am using PSoC 6 BLE Pioneer Kit. regarding my application, I need to have a digital output on P8[0] to P8[8] but it didn't work I tried the same program on other ports like P5[0] to P5[6] I got the digital output and it works fine. since I need a high number of digital output in my work, how can I make P8 work?
Show LessHello
This is the first time I have made a custom PCB for PSOC-6 device. I had been using PSOC-4 and 5 till date. Mistakenly the VDD_NS pin has been connected to GND instead of 3.3V. I am using Kitprog to program the device using SWD however I get a programming error. The device number is CY8C6137BZI-F54.
- Is it OK let the VDD_NS pin at 0V if we configure to use the LDO instead of SIMO buck?
- Is it possible that the programming error is because of the VDD_NS pin being connected to 0V instead of 3.3V? (I have configured the system settings for LDO and not SIMO)
Thank you
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