PSoC™ 6 Forum Discussions
Hi.
I saw an article about collaborating with Picovoice.
https://www.infineon.com/cms/en/about-infineon/press/market-news/2021/INFCSS202110-007.html
Can this program the Picovoice sample code on the PSoC 6 evaluation board?
If so, where can I get the sample code?
If you want to evaluate in a different way, could you tell me how?
Best Regards.
Show LessI trying to make OSB (on screen display) for analog video (NTSC format) with 640X480 pixels resolution.
To synchronize to the external video i using external board to catch the sync pulses from analog video, every sync type connected to GPIO and to ISR.
The horizontal sync pulse is active once a 64uSec, so once 64uSec trigger the DMA programmatically and send the data to Control register which connected GPIO
(the GPIO connected to the video line via diode).
The GPIO rise the voltage (distortion) at specific point of time and it make the pixel white. With this method i can draw on the analog video.
At LP5 (CY8C5888LTI-LP097) -----
This method work and stable, but i facing two main problems:
1)At max clock (PLL at 80Mhz) i can reach max 464 pixels per line (for each 52uSec of visible line 464 distortions on the video line) - need to have 640 distortions for 52uSec piece of time.
2)I can't reach 640X480 buffer size (640X480 /1024 =300KB ) - i use Byte per pixel (CY8C5888LTI-LP097 is max 64KB SRAM).
At Posc 6 (CY8C6347BZI-BLD53) -----
To overcome LP5 problems i try to use Posc 6 (CY8C6347BZI-BLD53) but i stuck with the DAM configurations, i see on the oscilloscope the Bytes i try to send, but
the rate is very slaw (8 Bytes per 500uSec), according to the datasheet the DMA use Clk_Slow , but i configured it to 100Mhz.
1-What could be the problem with the configuration?
2-It seems that the Bytes are not stable at this slow rate (although using an old oscilloscope..)
3-At lp5 the DMA cannot access to all the SRAM, is it the same with PSOC6?
4-Is there any way to send bit by bit instead of byte?
Hi,
There are differante kind of PSoC 6. 61, 62, 63.
What are the differances?
Thanks
Shmuel
I'm try to set up the ADC using the device configurator, as follow:
- Vref = Internal Reference (from AREF Resource) 1.2V
- No. of channel =2
-Ch0 Vplus= P10.0, Cho Vminus=AREF vref
-Ch1 Vplus= P10.1, Cho Vminus=AREF vref
After I set this the Notice list Show: "Task: ADC clock frequency, 2000000, is out of the supported range (1.7 to 1.8 MHz). [CY8C6244LQI-S4D92: 12-bit SAR ADC 0 [clk_freq_display]]"
Then I try to set the "Clock Select" from "Deep Sleep Clock" to "Peripheral Clock Divider" , and "Clock" as "8 bit Divider 2 clk" , the Clock frequency shows as 1.786MHz +/- 2.4%.
But the notice list shows Task: "Resource 'amuxbus_a_sar' is overused between nets 'csd[0].csd[0]:sense:3, pass[0].saradc[0].sar[0]:Vminus:0, pass[0].saradc[0].sar[0]:Vminus:1' [CY8C6244LQI-S4D92: Routing Results]"
How can I solve this?
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Hello,
I am currently working on a project with classmates that involves using the PSoC 6. We are hooking up the PSoC to a digital-multimeter circuit, the MAX134 chip. The MAX134 uses a bidirectional data bus (4 pins), as well as address lanes to communicate with a microprocessor. We are trying to setup bidirectional pins in our top design, and it seems that whatever status we set to our pins when we write to the MAX134, it never gives up the bus to the MAX134 to return data to us.
How would we give up authority on the bus to the other chip? I've seen information about setting different drive modes for the pins, but I don't know which is best for this application. Thanks.
I'm trying to understand, via the Architecture TRM, Registers TRM, and the PDL documentation how the Trigger Mux's connect to the PWM Trigger inputs.
I can see that there are 2 Trigger Mux groups, 2 and 3, that connect into the TCPWM's. It looks like the TCPWMx_GRPy_CNTz_TR_IN_SEL1 register is used to select the trigger source for the START signal to the TCPWM. It looks like I can chose between 139 possible trigger choices per figure 25-3 in the TRM. It seems like I can pick the same trigger for each of the counters I might want to control. I want to understand in more detail what is happening
1) Trigger group 2 vs Trigger group 3, which one is used and where is this documented?
2) There are 28 outputs from those 2 trigger groups. How are they routed to the PWM's, where is this documented in the architecture or where is a register controlling this?
3) I cannot understand Table 29-2 in the TRM, there is no indication of what registers control this "selection"?
The PDL documentation shows that I can use Cy_TrigMux_SwTrigger to software trigger all my TCPWM's to START at the same time, but I am unclear how this occurs without understanding the mux connections from the Trigger mux to the individual TCPWM's. Please help my understanding.
And note, this is for the 6xx4 family which is the Ver 2 style of TCPWM and muxing.
Show LessHello,
using Device configurator and QSPI configurator how could i generate a flashloader for Modbustoolbox of external memory?
does the .c/.h file generated used by the tool or does it generates a .elf file to be downloaded in RAM the case in IAR and MDK-ARM?
Thanks in advance.
Show LessBecause one of our customer asked, We are looking for the PSoC MCU which can handle below features.
1. OpenMV feature supported
2. MIPI feature supported
3. Camera feature supported
I cannof find a solution which meet above feature in Infineon Web site.
Please guide us to find a solution.
Many Thanks
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