PSoC™ 6 Forum Discussions

Hi Infineon Community:

I tried to flash my CY8CKIT-062S2-43012 evaluation board with the "Machine_Learning_Imagimob_MTBML_Deploy" and also the "Machine_Learning_Imagimob_MTBML_Collection Data" on ModusToolbox 3.1. I got the following error on the console when going to debug mode. 

***************************************
** Silicon: 0xE453, Family: 0x102, Rev.: 0x12 (A1)
** Detected Device: CY8C624ABZI-S2D44
** Detected Main Flash size, kb: 2048
** Flash Boot version: 3.1.0.378
** Chip Protection: NORMAL
***************************************
Info : [psoc6.cpu.cm4] Cortex-M4 r0p1 processor detected
Info : [psoc6.cpu.cm4] target has 6 breakpoints, 4 watchpoints
Info : starting gdb server for psoc6.cpu.cm0 on 3332
Info : Listening on port 3332 for gdb connections
Info : starting gdb server for psoc6.cpu.cm4 on 3333
Info : Listening on port 3333 for gdb connections
Info : SWD DPIDR 0x6ba02477
Info : kitprog3: acquiring the device (mode: reset)...
[psoc6.cpu.cm0] halted due to debug-request, current mode: Thread
xPSR: 0x41000000 pc: 0x00000190 msp: 0x080ff800
** Device acquired successfully
** psoc6.cpu.cm4: Ran after reset and before halt...
[psoc6.cpu.cm4] halted due to debug-request, current mode: Thread
xPSR: 0x01000000 pc: 0x0000012a msp: 0x080ff800
Started by GNU MCU Eclipse
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : accepting 'gdb' connection on tcp/3333
Info : New GDB Connection: 1, Target psoc6.cpu.cm4, state: halted
Warn : Prefer GDB command "target extended-remote :3333" instead of "target remote :3333"
semihosting is enabled
Warn : No RTOS could be auto-detected!
Warn : No RTOS could be auto-detected!
Verifying region (0x10000000, 6352)... Match
Verifying region (0x10002000, 50376)... Match
Info : All data matches, Flash programming skipped
Info : SWD DPIDR 0x6ba02477
Info : SWD DPIDR 0x6ba02477
Error: Failed to write memory at 0xe0001Polling target psoc6.cpu.cm4 failed, tryin04c
g to reexamine
Info : [psoc6.cpu.cm4] Cortex-M4 r0p1 processor detected
Info : [psoc6.cpu.cm4] target has 6 breakpoints, 4 watchpoints
Info : [psoc6.cpu.cm0] external reset detected
Info : [psoc6.cpu.cm4] external reset detected
Info : SWD DPIDR 0x6ba02477
Error: Failed to write memory at 0xe000103c
Polling target psoc6.cpu.cm4 failed, trying to reexamine
Info : [psoc6.cpu.cm4] Cortex-M4 r0p1 processor detected
Info : [psoc6.cpu.cm4] target has 6 breakpoints, 4 watchpoints
Info : psoc6.cpu.cm4: Waiting up to 10.0 sec for valid Vector Table address...
Info : psoc6.cpu.cm4: Vector Table found at 0x10002000
Info : psoc6.cpu.cm4: bkpt @0x10002371, issuing SYSRESETREQ
Info : SWD DPIDR 0x6ba02477
[psoc6.cpu.cm4] halted due to breakpoint, current mode: Thread
xPSR: 0x61000000 pc: 0x10002370 msp: 0x080ff800, semihosting
Info : [psoc6.cpu.cm0] external reset detected

These are the two main errors I found:

Error: Failed to write memory at 0xe000104c

Error: Failed to write memory at 0xe000103c

I have to mention that I tested with the hello world SDK and I didn´t have any issues. I don't know if the issue is related to the size of the project or a problem with the internal memory of the MCU.

I have looked in the community for similar questions, but they didn´t help me solve my issue.

https://community.infineon.com/t5/PSoC-6/Error-Failed-to-read-memory-at-0xfffff000-Info-SWD-DPIDR-0x...

https://community.infineon.com/t5/ModusToolbox/Modus-Toolbox-3-0-programming-error-quot-Failed-to-wr...

Regards,

I have seen that PSOC  6 has PDM -> PCM Converter
but I would like to know if the PSOC can handle PCM signals 
and if it did, which are the pins it would use

Hi PSoC Community, I have several questions regarding a SCB in SPI slave (receiving data from a 32 bit ADC) and DMA transfer from the SPI slave RX fifo buffer to a double buffer setup on the PSoC. The data rate output from the ADC is 16.384 Mbps I am unsure about a few things:

1. Firstly, I am setting the 'Data Rate (kbps)' in the SCB in slave mode to be 16384. Shouldn't this be sufficient to determine the clock that operates the SCB? I dont understand why we need to specify another that drives the block. Also what value should I set the block clock to be? Currently this is set to be 100 MHz (the peripheral clock) which is derived from the FLL.

2. Can someone please confirm that setting the SCB SPI RX data width to be 16 is OK? As I mentioned above, the ADC generates 32 bit data, so the CS signal remains low for 32 bits of the transfer. Does the SCB in slave mode store the single 32 bits as two 16 bit values in the SCB RX fifo buffer if the CS signal remains low for the 32 bits of the transfer? (as the maximum RX data width for the SCB SPI block is 16). Unfortunately I am unable to control the SPI master CS line to drive high and then low again in the middle of the 32 bit transfer.

3. Finally when the SCB RX Fifo buffer is full, I have set up the SCB to trigger a DMA transfer. The issue I have here is that I am unsure what to set the 'Data transfer width' in the DMA descriptor to be. Intuitively I thought it should be Halfword (2 bytes) to Halfword, where the source is the SCB RX Fifo buffer which is set to have a data width of 16 bits, and the destination also halfword, as I have allocated uint16_t memory block (destination). However, it seems that the source (the SCB RX Fifo) must be set to be 'Word' for the program to compile and run. Can someone please explain why this is? Also there are Word to Word (masked) settings in the selection, can someone also explain what these are for? The documentation is really poor! P.S. I then combine two 16 bit values into a single 32 bit value after the DMA transfer to memory. Any help is appreciated.