PSoC™ 6 Forum Discussions

I want to write a port in parallel as I can do.
I used the CY_GPIO_Port_Init function (gipoport, config); but how do I write the data ?.
with PSOC 5 use: void portxxx_Write (uint8 value);

Hi All,

I'll start a PSoC61 project soon. The PSoC61 features I will need are:

* SPI

* I2C

* USB UART (console)

* USB (need to create my own endpoints for my own protocol)

* Bootloader

* GPIO (digital, analog)

* GPIO interrupts

* Eventually I'll need to use UDB features using PSoC Creator... and I plan to integrate the generated "blob" manually.

Should I use Zephyr? (Does Zephyr support all the above mentioned features)

Or should I go with ModusToolbox + PDL?

What the official (and unofficial) recommendation for new PSoC6 projects?

Many thanks!

I had previously asked, " Does every PSoC 62 support a hosted WiFi/BLE module (SDIO) interface?  "    

From that response, I had concluded a PSoC 62 needed UDBs to support an SDIO interface to support a hosted radio module.

I now see, there are only eight (8) PSoC 62 devices in the PSoC 6 product selector (https://www.infineon.com/cms/en/product/microcontroller/32-bit-psoc-arm-cortex-microcontroller/) that are identified as having UDBs:

CY8C6245FNI-S3D71T
CY8C6245LQI-S3D62
CY8C6247BZI-AUD54
CY8C6247BZI-D34
CY8C6247BZI-D54
CY8C6247BZI-D54T
CY8C6247FDI-D32T
CY8C6247FDI-D52T

There is an additional PSoC 62 paired with WiFi/BLE modules on a kit that isn't identified as having UDBs:

CY8C624ABZI-S2D44 in CY8CKIT-062S2-43012

Are there other criteria, besides the noted presence of UDBs that allow a PSoC 6 to interface with a Hosted WiFi/BLE module?

Greg

According to the previous post, the bin file was successfully created.
https://community.infineon.com/t5/PSoC-6/How-to-create-bin-file-in-Modus-Toolbox/m-p/340151#M12228

But in the following example, an error occurs when compiling.

- CY8CKIT-062-WIFI-BT
- Basic_Device_Firmware_Upgrade_boolader_cm4

There seems to be a problem if there are spaces in the folder, but my folder does not contain spaces.
I don't know how to solve it.

Regards,
YS

Dears,
I'm using CY8CKIT-062-WIFI-BT.

If I erase the flash with Cypress Programmer and read it, I can see that the hex file is filled with 0x00.
Generally, I know that flash becomes 0xFF after erase, but PSoC6 becomes 0x00?
I wonder what (0x00 or 0xFF) to fill in the space between the booloader and the application when using the hex2bin utility.

Best Regards,
YS

We are working on the building  of an Agristation for agriculture diagnostics so we want to know how many communication protocols  SCB's can be implimented in this  Development kit .Then also it states that this CY8CKIT-062-WIFI-BT has 56 programmable Digital blocks and 7 programmable Analog blocks  but where are the GPIO's that can be used for the TCPWM,Universal Digital Blocks and these SCB's and then ADC,OP amp's.Could you please help us about this so that we can make a blue print of How many sensors can be interfaced with this development kit.

Where can I find more detail for selecting a MHz XTAL for Bluetooth_LE  or  BLE ECO for PSoC 63?

Table 58 in the CY8C63x6, CY8C63x7 datasheet identifies two oscillators for the BLE ECO input of a PSoC 63: 16 MHz and 32 MHz.

The BLE ECO appears to be the connection to the XI/XO pins referred to in Figure  5 of the same document.

There’s a single note in AN218241, PSoC 6 MCU Hardware Design Considerations regarding the BLE ECO that states: "It should be noted that the ECO available as part of the BLE radio has its own pins (XI and XO). You can add the load capacitor, crystal accuracy, and startup time details in the AltHF clock configure window as shown in Figure 9. External load capacitors for the BLE ECO are not required."  Again here, it doesn't state any difference in the ECO frequency selected. Does the frequency of the crystal connected to the XI/XO pins matter as long as it matches the frequency identified in the brown box of Figure 9?

Greg

Hi.

I'm trying to use the HAL System Power Management library to put the CM4 to sleep. So far, I've had no luck, and as I have found too many times, there is very little documentation available, and no examples. What documentation exists (e.g. Architecture TRM) is unclear, even suggesting that only masked interrupts can wake up a sleeping CPU.

Here's the environment:

• PSoC 63 with BLE in a custom board.
  • MTB 2.3.0 
  • BSP 2.3.0
  • PDL 2.3.0
  • HAL 2.1.0
• CM4 and CM0+ running FreeRTOS
• Several peripherals in use (BLE, I2C, UART, SPI, RTC, TWPCM, etc.)

1. I registered four callbacks using cyhal_syspm_register_callback(). 
2. I call cyhal_syspm_sleep().
3. The four callbacks are called with state set to CYHAL_SYSPM_CB_CPU_SLEEP and mode set to CYHAL_SYSPM_CHECK_READY. All callbacks return true.
4. The four callbacks are called again with state set to CYHAL_SYSPM_CB_CPU_SLEEP, but this time mode set to CYHAL_SYSPM_BEFORE_TRANSITION.
5. The four callbacks are immediately called a third time with state set to CYHAL_SYSPM_CB_CPU_SLEEP, but this time mode set to CYHAL_SYSPM_AFTER_TRANSITION.

The first problem is that the CPU either doesn't sleep, or wakes up immediately. I disable the RTOS SysTick interrupt in one of the callbacks. I also disable several other peripheral interrupts, and turn off the BLE stack, none of which has made a difference. It's likely that some interrupt is firing, but I can't think of a good way to determine which is the culprit.

The second problem is that the stated behavior, namely that the callbacks are called on wakeup (CYHAL_SYSPM_AFTER_TRANSITION) in the reverse of the order in which they are called on sleep (CYHAL_SYSPM_CB_CPU_SLEEP) does not match the observed behavior.
Callbacks are always called in the same order, even when one of the callbacks returns false in response to CYHAL_SYSPM_CHECK_READY.

Has anyone successfully used cyhal_syspm_sleep() to put one of the CPUs to sleep?

Thanks,

-Nick

Hello,

I am using modustoolbox 2.4 with 256k flash PSoC6 controller which has CM0+ and CM4 cores. I want that cores should be deepsleep mode. I am calling 

"Cy_SysPm_CpuEnterDeepSleep(CY_SYSPM_WAIT_FOR_INTERRUPT); " from CM4 core. Would CM0+ core also enters into deepsleep? I am expecting current consumption in range of 10uA, but I am measuring around ~2mA. Could you suggest?

How can can I check that CM0+ is in deepsleep or not? I also checked Switching_Power_Modes example code. I am not able to locate the main function of CM0+ core. There is only startup function as below:

Where is main function of CM0+ in Modustoolbox example code.